Efficient model sharing for scalable collaborative classification

We propose a novel collaborative approach for document classification, combining the knowledge of multiple users for improved organization of data such as individual document repositories or emails. To this end, we distribute locally built classification models in a network of participating users, and combine the shared classifiers into more powerful meta models. In order to increase the propagation efficiency, we apply a method for selecting the most discriminative model components and transmitting them to other participants. In our experiments on four large standard collections for text classification we study the resulting tradeoffs between network cost and classification accuracy. The experimental results show that the proposed model propagation has negligible communication costs and substantially outperforms current approaches with respect to efficiency and classification quality.     

Open Mobile Alliance (OMA) security layer: Architecture, implementation and performance evaluation of the integrity unit

Security has become a very critical issue in the provision of mobile services. The Open Mobile Alliance (OMA) has specified a powerful security layer, the WTLS. In this paper, a VLSI architecture for the implementation of the WTLS integrity unit is proposed. The proposed architecture is reconfigurable in the sense that operates in three different modes: as Keyed-Hash Authentication Code (HMAC), as SHA-1 and MD5 hash functions, according to WTLS specifications. This multi-mode operation is achieved due to the reconfigurable applied design technique in the proposed architecture, which keeps the allocated area resources at a minimized level. The proposed architecture achieves high speed performance, due to the pipeline designed architecture. Especially, SHA-1 operation achieved throughput is equal to 1,7 Gbps, while MD5 operation mode bit rate is equal to 2,1 Gbps. The proposed architecture has been integrated by using VHDL and has been synthesized placed and routed in an FPGA device. Comparisons with related hash functions implementations have been done in terms of throughput, operating frequency, allocated area and Area-Delay product. The achieved performance of the SHA-1 operation mode is better at about 14–42 times compared with the other conventional works. In addition, MD5 performance is superior to the other works at about 6–18 times, in all of the cases. The proposed Integrity Unit is a very trustful and powerful solution for the WTLS layer. In addition, it can be integrated in security systems which are used for the implementation networks for wireless protocols, with special needs of integrity in data transmission. Nicolas Sklavos, Ph.D.: He is a Ph.D. Researcher with the Electrical and Computer Engineering Department, University of Patras, Greece. His interests include computer security, new encryption algorithms design, wireless communications and reconfigurable computing. He received an award for his Ph.D. thesis on “VLSI Designs of Wireless Communications Security Systems” from IFIP VLSI SOC 2003. He is a referee of International Journals and Conferences. He is a member of the IEEE, the Technical Chamber of Greece and the Greek Electrical Engineering Society. He has authored or co-authored up to 50 scientific articles in the areas of his research. Paris Kitsos, Ph.D.: He is currently pursuing his Ph.D. in the Department of Electrical and computer Engineering, University of Patras, Greece. He received the B.S. in Physics from the University of Patras in 1999. His research interests include VLSI design, hardware implementations of cryptography algorithms, security protocols for wireless communication systems and Galois field arithmetic implementations. He has published many technical papers in the areas of his research. Epaminondas Alexopoulos: He is a student of the Department of Electrical and Computer Engineering, University of Patras, Greece. His research includes hardware implementations, mobile computing and security. He has published papers in the areas of his research. Odysseas Koufopavlou, Ph.D.: He received the Diploma of Electrical Engineering in 1983 and the Ph.D. degree in Electrical Engineering in 1990, both from University of Patras, Greece. From 1990 to 1994 he was at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, University of Patras. His research interests include VLSI, low power design, VLSI crypto systems and high performance communication subsystems architecture and implementation. He has published more than 100 technical papers and received patents and inventions in these areas.     

FEC in optical communications - A tutorial overview on the evolution of architectures and the future prospects of outband and inband FEC for optical communications

The recent establishment of the 10/40 Gbps technology in DWDM optical links heralds a new era of bandwidth abundance, in response to an explosive growth of services provided through the Internet. Forward error correction (FEC) is one of the key-enabling elements in this long-awaited achievement. Borrowed from the wireless world, FEC was initially introduced in wavelength-division multiplex (WDM) optical-systems to combat amplified spontaneous emission (ASE), a form of noise native in optical amplifiers (OAs). These first generation FEC systems have been associated with a coding-gain of approximately 6 dB. However, as transmission rates gradually scaled towards 10 Gbps, other optical-impairments gained in significance, primarily nonlinear (NL) effects but also chromatic-dispersion (CD) and polarization mode dispersion (PMD). FEC turned out to be invaluable in mitigating these impairments as well     

Improved throughput bit-serial multiplier for GF(2) fields

High throughput is a crucial factor in bit-serial GF(2^m) fields multiplication for a variety of different applications including cryptography, error coding detection and computer algebra. The throughput of a multiplier is dependent on the required number of clock cycles to reach a result and its critical path delay. However, most bit-serial GF(2^m) multipliers do not manage to reduce the required number of clock cycles below the threshold of m clock cycles without increasing dramatically their critical path delay. This increase is more evident if a multiplier is designed to be versatile. In this article, a new versatile bit-serial MSB multiplier for GF(2^m) fields is proposed that achieves a 50% increase on average in throughput when compared to other designs, with a very small increase in its critical path delay. This is achieved by an average 33.4% reduction in the required number of clock cycles below m. The proposed design can handle arbitrary bit-lengths upper bounded by m and is suitable for applications where the field order may vary.     

The GMAP: a versatile tool for physical data independence

Physical data independence is touted as a central feature of modern database systems. It allows users to frame queries in terms of the logical structure of the data, letting a query processor automatically translate them into optimal plans that access physical storage structures. Both relational and object-oriented systems, however, force users to frame their queries in terms of a logical schema that is directly tied to physical structures. We present an approach that eliminates this dependence. All storage structures are defined in a declarative language based on relational algebra as functions of a logical schema. We present an algorithm, integrated with a conventional query optimizer, that translates queries over this logical schema into plans that access the storage structures. We also show how to compile update requests into plans that update all relevant storage structures consistently and optimally. Finally, we report on experiments with a prototype implementation of our approach that demonstrate how it allows storage structures to be tuned to the expected or observed workload to achieve significantly better performance than is possible with conventional techniques. Edited by Matthias Jarke, Jorge Bocca, Carlo Zaniolo. Received September 15, 1994 / Accepted September 1, 1995     

A motion control framework for autonomous water sampling and swing-free transportation of a multirotor UAV with a cable-suspended mechanism

In this work, we present an end-to-end solution for autonomous water sampling by utilizing an unmanned aerial vehicle (UAV) with a cable-suspended mechanism. Towards this direction, a sampling mechanism is initially designed in such a manner that the water sampling success ratio is maximized. However, the disturbances, acting on the submerged mechanism due to the water flow during the sampling procedure, impede the stabilization of the vehicle above the desired sampling position. Consequently, to achieve the precise hovering of the UAV, the vehicle's sensor suite is further augmented with a load cell, a depth sensor, an ultrasonic sensor, and a camera. The respective measurements are appropriately fused by employing an extended Kalman filter (EKF). Hence, an estimate of the disturbances is available in real-time and is incorporated into a Model Predictive Control scheme which compensates for the aforementioned disturbances and stabilizes the vehicle above the sampling location. Finally, a complete water sampling mission entails the safe and swing-free transportation of the mechanism towards the sampling location and, then, to a position where the collected samples are postprocessed by human operators. Consequently, a model predictive controller is employed which ensures the navigation of the vehicle to the desired waypoints while minimizing the swinging motion of the mechanism. The state of the mechanism is obtained by fusing measurements provided by the load cell and the camera with an EKF. The performance of the proposed framework, which aims to address all the aspects of a water sampling mission, is demonstrated through real experiments with an octorotor.