Electrical characteristics of lead-free Mn-doped BiFeO3–SrTiO3 thin films deposited on silicon substrate using pulsed laser deposition

Journal of Materials Science: Materials in Electronics - Lead-free 0.4(BiFe0.995Mn0.005O3)–0.6(SrTiO3) thin films were deposited on boron-doped silicon (p-Si) through pulsed laser deposition....     

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

The contact resistance of field effect transistors based on pentacene and parylene has been investigated by experimental and numerical analysis. The device simulation was performed using finite element two-dimensional drift-diffusion simulation taking into account field-dependent mobility, interface/bulk trap states and fixed charge density at the organic/insulator interface. The width-normalized contact resistance extracted from simulation which included an interface dipole layer between the gold source/drain electrodes and pentacene was 91 k??cm. However, contact resistance extracted from the simulation, without consideration of interface dipole was 52.4?k??cm, which is about half of the experimentally extracted 108?k??cm. This indicates that interface dipoles are critical effects which degrade performances of organic field effect transistors by increasing the contact resistance. Using numerical calculations and circuit simulations, we have predicted a 1?MHz switching frequency for a 1???m channel length transistor without dipole interface between gold and pentacene. The transistor with dipole interface is predicted, via the same methods, to exhibit an operating frequency of less than 0.5?MHz.     

A novel low temperature integration of hybrid CMOS devices on flexible substrates

In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180 °C and 120 °C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm²/V s, respectively. Threshold voltages (V_t) are 1.14 V for nMOS and −1.89 V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.     

Fabrication of Relaxer-Based Piezoelectric Energy Harvesters Using a Sacrificial Poly-Si Seeding Layer

The effect of a polycrystalline silicon (poly-Si) seeding layer on the properties of relaxor Pb(Zr_0.53,Ti_0.47)O₃–Pb(Zn_1/3,Nb_2/3)O₃ (PZT–PZN) thin films and energy-harvesting cantilevers was studied. We deposited thin films of the relaxor on two substrates, with and without a poly-Si seeding layer. The seeding layer, which also served as a sacrificial layer to facilitate cantilever release, was found to improve morphology, phase purity, crystal orientation, and electrical properties. We attributed these results to reduction of the number of nucleation sites and, therefore, to an increase in relaxor film grain size. The areal power density of the wet-based released harvester was measured. The power density output of the energy harvester with this relaxor composition and the poly-Si seeding layer was 325 μW/cm².     

Hybrid CMOS thin-film devices based on solution-processed CdS n-TFTs and TIPS-Pentacene p-TFTs

Fabrication and characterization of integrated hybrid complementary metal oxide semiconductor devices (CMOS) using 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-PC) and cadmium sulfide (CdS) as the active layers deposited using solution based processes are demonstrated. The n- and p-type thin film transistors (TFTs), inverters, and NAND gate devices were fabricated using photolithography-based techniques. The hybrid CMOS technology demonstrated is compatible with large-area and mechanically flexible substrates given the low temperature processing (<100 °C) and scalable design. The integrated n- and p-type devices show saturation mobilities of 15 and 0.02 cm²/V s, respectively. The inverters exhibited a DC gain of ≈52 V/V with full rail-to-rail switching. The NAND logic gates switch rail-to-rail with a transition point of V_DD/2.     

Low-temperature deposition of hafnium silicate gate dielectrics

The physical and electrical properties of hafnium silicate (HfSi/sub x/O/sub y/) films produced by low-temperature processing conditions (/spl les/150/spl deg/C) suitable for flexible display applications were studied using sputter deposition and ultra-violet generated ozone treatments. Films with no detectable low-/spl kappa/ interfacial layer were produced. Rutherford backscattering spectroscopy, X-ray photoelectron spectroscopy, and high-resolution transmission electron microscopy were used to determine the composition, chemical bonding environment, thickness, and film interface. The electrical behavior of the as-deposited and annealed hafnium silicate films were determined by current-voltage (I--V) and capacitance-voltage (C--V) measurements.     

Enhancement of the photochromic and thermochromic properties of molybdenum oxide thin films by a cadmium sulfide underlayer

We investigated the photochromic and thermochromic behavior of amorphous MoO₃ films prepared by thermal evaporation of MoO₃ powder on glass and glass/CdS substrates. We used the cadmium sulfide as a carrier charge injector to produce higher color center concentrations in the MoO₃ film. The semiconductor CdS (cadmium sulfide) film was synthesized using the chemical bath deposition technique. The glass/MoO₃ and glass/CdS/MoO₃ films were subjected to tungsten lamp (100 W) exposure times of 45 to 180 min to study the photochromic sensitivity of the films. To study the thermochromic properties, samples were thermally annealed at temperatures ranging from 100 to 250 °C during 2 h. X-ray diffraction studies show that the CdS films were polycrystalline, and the oxide films were amorphous. Optical absorption measurements showed the presence of an absorption band centered around 850 nm due to the formation of color centers. Concentrations of these were calculated using the Smakula equation. Results indicate that the addition of CdS films enhances the photochromic and thermochromic properties of MoO₃. Photochromism is more effective than thermochromism in generating color centers when using CdS as a charge carrier.     

Effect of interfacial features on the mechanical and electrical properties of rGO/Al composites

This study investigates the effect of interfacial features on the mechanical and electrical properties of reduced graphene oxide (rGO)/aluminum (Al) composites. The composites were fabricated using a hybrid process that includes chemical and mechanical methods. First, GO was uniformly dispersed on the surface of Al powder via a solution process. A strong interface was formed between GO and Al via several chemical bonds by using polyvinyl alcohol (PVA) as an organic binder during the solution process. Then, GO was thermally reduced to rGO, wherein the interfacial features were varied according to the atmosphere (vacuum or H₂(10%)/N₂(90%) mixed gas). Subsequently, rGO was mechanically embedded and further dispersed within soft Al powder through the plastic deformation of Al. Vacuum was found to be more effective than the mixed gas at removing functional groups containing oxygen in GO and therefore generated a tighter interface. As a result, the composites containing rGO that were reduced under vacuum showed higher strength and lower ductility compared with those reduced under the mixed gas. Conversely, the interfacial features rarely affected the electrical conductivity of the composites because the electrical conductivity of rGO was considerably lower than that of Al. Consequently, compared with their monolithic counterparts, the composites containing only 0.2 vol% rGO showed a 374-MPa yield strength without a significant loss of electrical conductivity, thereby demonstrating their potential feasibility in electrical and electronic applications.