Fabrication and Room-Temperature Single-Charging Behavior of Self-Aligned Single-Dot Memory Devices

Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application     

Self-aligned silicon-on-insulator nano flash memory device

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal floating gate embedded in the gate oxide. The length, width and height of the nanocrystal are 10, 10 and 20 nm, respectively. As long as the control gate voltage does not exceed ±2V, the device behaves like a thin and narrow P-channel MOSFET. When a voltage of −5 or +5 V is applied to the control gate at room temperature, holes are injected into the floating gate or removed from it, respectively. This effect induces a persistent shift of the threshold voltage of the device, which acts as a miniature EEPROM.     

Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories

We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimensions and position of each floating gate are well-defined and controlled. The devices exhibit a long retention time and single-electron injection at room temperature.     

A Simple Method for Measuring Si-Fin Sidewall Roughness by AFM

The gate oxide reliability and the electrical behavior of FinFETs are directly related to the surface characteristics of the fin vertical sidewalls. The surface roughness of the fin sidewalls is one of the most important structural parameters to be monitored in order to optimize the fin patterning and postetch treatments. Because of the nanometer-scale dimensions of the fins and the vertical orientation of the sidewall surface, their roughness measurement is a serious challenge. In this paper, we describe a simple and effective method for measuring the sidewall morphology of silicon fins by conventional atomic force microscopy. The present methodology has been employed to analyze fins as etched by reactive ion etching and fins repaired by sacrificial oxidation. The results show that sacrificial oxidation not only reduces the roughness of the sidewalls, but also rounds the top corners of silicon fins. The present method can also be applied to characterize sidewall roughness of other nanostructures and materials such as the polysilicon gate of transistors or nanoelectromechanical beams.     

Fluorination of suspended graphene

Nano Research - Suspended graphene is exposed to different fluorine-containing species produced by a plasma source fed with CF4 precursor gas. We investigate the fluorination process by selecting...     

Anomalous moire pattern of graphene investigated by scanning tunneling microscopy： Evidence of graphene growth on oxidized Cu（111）

The growth of graphene on oriented （111） copper films has been achieved by atmospheric pressure chemical vapor deposition. The structural properties of as-produced graphene have been investigated by scanning tunneling microscopy. Anomalous moir6 superstructures composed of well-defined linear periodic modulations have been observed. We report here on comprehensive and detailed studies of these particular moir6 patterns present in the graphene topography revealing that, in certain conditions, the growth can occur on the oxygen-induced reconstructed copper surface and not directly on the oriented （111） copper film as expected.     

Characterization of ultrathin SOI film and application to short channel MOSFETs

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3?nm. The etch rate is precisely controlled at 0.11???s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15?nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30?nm, featuring state-of-the-art current drive performance.     

Comparative study of erbium disilicide thin films grown in situ under ultrahigh vacuum or ex situ with a capping layer

Erbium disilicide (ErSi_2-x) thin films grown by two different techniques are compared using a variety of characterization techniques, both electrical and physical. The first technique involves Er deposition and annealing under ultrahigh vacuum and the second one focuses on Ti/Er/Si(100) stacks evaporated under high vacuum and heated ex situ by rapid thermal annealing. Crystalline phase identification by X-ray diffraction reveals the formation of ErSi_2-x for all the studied samples. Cross-sectional transmission electron microscopy shows that the Ti cap transforms into Ti-Si compounds. The efficient stripping of the capping layer is also demonstrated. Atomic force microscopy evidences the formation of inverted pyramidal defects in both cases, with some improvement for the Ti-capped samples. X-ray photoelectron spectroscopy depth profiles show that the ErSi_2-x films and the ErSi_2-x/Si interfaces are oxygen-free. The extracted Schottky barrier height of ErSi_2-x/n-Si contacts lies around 0.3 eV notwithstanding the annealing temperature or the growth technique. It thus demonstrates a route to form ErSi_2-x thin films that advantageously compares with reference ultrahigh vacuum samples with less stringent fabrication conditions.