Eliminating memory for fragmentation within partitionable SIMD/SPMDmachines

Efficient data layout is an important aspect of the compilation process. A model for the creation of perfect memory maps for large-scale parallel machines capable of user-controlled partitionable single-instruction-multiple data/single-program-multiple data (SIMD/SPMD) operation is developed. The term perfect implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. A major constraint on solving this problem is based on the single program nature of both the SIMD and SPMD modes of parallelism. It is assumed that all processors within the same submachine used identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create perfect memory maps, and results are applied to several partitionable interconnection networks     

A new method for manufacturing nanostructured electrodes on glass substrates

The present paper describes a new method for manufacturing a nanostructured porous layer of TiO₂ on a conducting glass substrate for use in a dye-sensitized photoelectrochemical cell. The method involves deposition of a layer of semiconductor particles onto a conducting substrate and compression of the particle layer to form a mechanically stable, electrically conducting, and porous nanostructured film at room temperature. Photoelectrochemical characteristics and morphology of the resulting nanostructured films are presented. The potential use of the new manufacturing method in the future applications of nanostructured systems is discussed.     

Crystallographic electron microscopy

We present a family of techniques for the transmission electron microscope that generate surface zone-axis patterns. These patterns display the variation of the diffracted-beam intensity as a function of the angle of the incident electrons. The conditions of the experiments are those of reflection high-energy electron diffraction at near grazing incidence. The techniques are: surface convergent-beam diffraction, a surface analogue of the Tanaka method and a modified double-rocking scheme. Experimental results are presented for diffraction from surfaces of MgO and MoS₂. We anticipate that surface zone-axis patterns (surface ZAPs) will become established as an important tool for surface characterization, especially when used in conjunction with high-resolution surface imaging and surface energy loss spectroscopy; surface ZAPs may be expected to play, in surface analysis, a role analogous to that played by convergent-beam diffraction in normal transmission electron microscopy.     

Putting it all together – Formal verification of the VAMP

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. A shorter version of this article with the title “Instantiating uninterpreted functional units and memory system: functional verification of the VAMP” appeared in [8]. The work reported here was done while all the authors were with Saarland University.     

Prognostic significance of color Doppler findings in head and neck tumors

This summary of the practice parameters describes the assessment, differential diagnosis, and treatment of children, adolescents, and adults who present with symptoms of attention-deficit/hyperactivity disorder. The rationales for specific recommendations are based on a review of the scientific literature and clinical consensus which is contained in the complete document. Assessment includes clinical interviews with the child and parents and standardized rating scales from parent and teachers. Testing of intelligence and academic achievement is usually required. Comorbidity is common. The cornerstones of treatment are support and education of parents, appropriate school placement, and psychopharmacology. The primary medications are psychostimulants, but antidepressants and alpha-adrenergic agonists are used in special circumstances. Other treatments such as behavior modification, school consultation, family therapy, and group therapy address remaining symptoms.     

Menstrual cycle and age: influence on parenchymal contrast medium enhancement in MR imaging of the breast

PURPOSE: To quantify how frequently mesenteric adenitis clinically mimics appendicitis and to determine its appearance at computed tomography (CT). MATERIALS AND METHODS: The medical records of 651 consecutive patients with an admission diagnosis of appendicitis were reviewed to determine how often mesenteric adenitis was the discharge diagnosis. The CT scans of a separate group of 18 patients with a discharge diagnosis of mesenteric adenitis were reviewed. These patients were part of a group of 100 consecutive patients prospectively evaluated with CT of the appendix for clinically suspected appendicitis. RESULTS: Fifty of 651 patients (7.7%) with an admission diagnosis of appendicitis had a discharge diagnosis of mesenteric adenitis. Mesenteric adenitis constituted 50 of the 252 (19.8%) discharge diagnoses other than appendicitis. All 18 CT scans of mesenteric adenitis showed three or more nodes that measured at least 5 mm in shortest axis clustered in the right lower quadrant, with a normal appendix identified. Eight patients had associated ileal or ileocecal wall thickening. CONCLUSION: Mesenteric adenitis is an important clinical mimic of appendicitis. It appears at CT as clustered, enlarged mesenteric lymph nodes with a normal appendix, and there may be associated ileitis or ileocolitis noted.     

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers     

Phase relations in the system ln-CulnS2

By DTA and x-ray diffraction the phase relations in the pseudobinary system In-CuInS₂ have been investigated. CuInS₂ hs a melting point of 1090° C and within this system there is a broad region of liquid immiscibility. A four phase invariant reaction exists at 633° C which is of the form: L₂ = L₁+ CuInS₂ + InS.