Ultrafast Electron–Phonon Coupling at Metal-Dielectric Interface

Energy transfer from photo-excited electrons in a metal thin film to the dielectric substrate is important for understanding the ultrafast heat transfer process across the two materials. Substantial research has been conducted to investigate heat transfer in a metal-dielectric structure. In this work, a two-temperature model in metal was used to analyze the interface electron and dielectric substrate coupling. An improved temperature and wavelength-dependent Drude–Lorentz model was implemented to interpret the signals obtained in optical measurements. Ultrafast pump-and-probe measurements on Au-Si samples were carried out, where the probe photon energy was chosen to be close to the interband transition threshold of gold to minimize the influence of non-equilibrium electrons on the optical response and maximize the thermal modulation to the optical reflectance. Electron-substrate interface thermal conductance at different pump laser fluences was obtained, and was found to increase with the interface temperature.     

Reducing cycle times in manufacturing and supply chains by input and service rate smoothing

A key performance parameter of a manufacturing network or supply chain is its cycle time; the time that a typical item spends in the network. A previous simulation study on a semiconductor assembly and test facility showed that cycle times could be reduced by having smooth input and service rates. This suggested that there is a “cycle time principle” that, for a system with a specified throughput or input rate, the shortest cycle times are obtained when the input and service rates do not vary over time. We prove that this principle is true for the M/G/1 and M/M/s queueing systems and Jackson networks. The analysis involves establishing several results on the concavity of waiting time probabilities and the convexity of expected waiting times and queue lengths, as functions of input and service rates. These results also have natural uses in other optimization problems.     

Development of Stretch Solder Interconnections for Wafer Level Packaging

A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.     

Disaster recovery planning in an automated manufacturingenvironment

Disasters may strike at any moment in any location. When they do, no distinction is made about the type of firm that is being affected, whether it is a bank or a manufacturing plant. Most firms do not plan for possible disasters, and those that do have typically focused on computer and data contingency planning. In this paper, the focus is shifted to incorporate disaster recovery planning for manufacturing enterprises, especially those that are automated. Automated manufacturing enterprises have characteristics that put them at an increased risk to disasters. The methodological framework proposed in this paper will aid manufacturing organizations and their managers in reducing the risks associated with unanticipated disasters. The framework is termed the “Manufacturing Operations Recovery and Resumption” model. Recommended activities and tools for effective management of this methodology are identified     

Relationships between multiaxial stress states and internal fracture patterns in sphere-impacted silicon carbide

Internal fracture patterns developed in silicon carbide cylindrical targets as a result of dynamic indentation (63–500 m/s) by tungsten carbide spheres are defined. Microscopy of recovered and sectioned targets delineate into three regions, each associated with distinct cracking modes, i.e., shallow cone macrocracking at and near the impact surface, steep interior cone macrocracks that radiate into the target from the impact region and local grain-scale microcracking directly underneath the impact region. The observed fracture patterns are found to maintain a noticeable degree of self-similarity upto the impact velocity of 500 m/s. Linear elastic analysis of the full (surface and interior) stress field developed under static (Hertz) contact loading delineate the target into four regions, based on the number of principal stresses that are tensile (none, 1, 2 or all 3). A strong correlation is found between the principal stress conditions within each region and the forms of cracking, their locations and orientations present therein. This correlation has a number of implications, including non-interaction of crack systems, which are discussed. Illustrative linear elastic fracture mechanics analyses are performed for three regions, and calculated and observed macrocrack lengths are found to be in reasonable agreement.     

Impact of power-supply noise on timing in high-frequency microprocessors

This paper analyzes the impact of power-supply noise on the performance of high-frequency microprocessors. First, delay models that take this noise into account are proposed for device-dominated and interconnect-dominated timing paths. For typical circuits, it is shown that the peak of the noise is largely irrelevant and that the average supply voltage during switching is more important. It is then argued that global differential noise can potentially have a greater timing impact than common-mode noise. Finally, realistic values for the model parameters are measured on a 2.53-GHz Pentium4 microprocessor using a 130-nm technology. These values imply that the power-supply noise present on the system board reduces clock frequency by 6.7%. The model suggests that the frequency penalty associated with this power-supply noise will steadily increase and reach 7.6% for the 90-nm technology generation.     

Plasma immersion ion implantation for SOI synthesis: SIMOX and ion-cut

We have demonstrated feasibility to form silicon-on-insulator (SOI) substrates using plasma immersion ion implantation (PIII) for both separation by implantation of oxygen and ion-cut. This high throughput technique can substantially lower the high cost of SOI substrates due to the simpler implanter design as well as ease of maintenance. For separation by plasma implantation of oxygen wafers, secondary ion mass spectrometry analysis and cross-sectional transmission electron micrographs show continuous buried oxide formation under a single-crystal silicon overlayer with sharp Si/SiO₂ interfaces after oxygen plasma implantation and high-temperature (1300°C) annealing. Ion-cut SOI wafer fabrication technique is implemented for the first time using PIII. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration and there are minimal effects by other residual ions on the ion-cut process. The physical mechanism of hydrogen induced silicon surface layer cleavage has been investigated. An ideal gas law model of the microcavity internal pressure combined with a two-dimensional finite element fracture mechanics model is used to approximate the fracture driving force which is sufficient to overcome the silicon fracture resistance.     

Fabrication and characteristics of tapes and test magnets made from Ag-Clad Bi-2223 superconductors

Pb_0.4Bi_1.8Sr₂Ca_2.2Cu₃O_x (Bi-2223) precursor powder was prepared by a solid-state reaction of carbonates and oxides of lead, bismuth, strontium, calcium, and copper, and the powder was then used to fabricate silver-clad tapes by the powder-in-tube technique. Transport critical current density (J_c) values>4×10⁴ A/cm² at 77K and 2×10⁵ A/cm² at 4.2 and 27K have been achieved in short tape samples. Long lengths of tape were tested by winding them into pancake coils. Recently, we fabricated a test magnet by stacking ten pancake coils, each containing three 16m lengths of rolled tape, and tested it at 4.2, 27 and 77K. A maximum generated field of 2.6 T was measured in zero applied field at 4.2K and the test magnet generated significant self-field in background fields up to 20 T. The results are discussed in this paper.     

A general enthalpy method for modeling solidification processes

In the present work, a general implicit source-based enthalpy method is presented for the analysis of solidification systems. The proposed approach is both robust and efficient. The performance of the method is illustrated by application to a number of problems taken from recent metallurgical literature.