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1.
A multistep imprinting process is presented for the fabrication of a bottom-contact, bottom-gate thin-film transistor (TFT) on poly(ethylene naphthalate) (PEN) foil by patterning all layers of the metal–insulator–metal stack by UV nanoimprint lithography (UV NIL). The flexible TFTs were fabricated on a planarization layer, patterned in a novel way by UV NIL, on a foil reversibly glued to a Si carrier. This planarization step enhances the dimensional stability and flatness of the foil and thus results in a thinner and more homogeneous residual layer. The fabricated TFTs have been electrically characterized as demonstrators of the here developed fully UV NIL-based patterning process on PEN foil, and compared to TFTs made on Si with the same process. TFTs with channel lengths from 5 μm down to 250 nm have been fabricated on Si and PEN foil, showing channel length-dependent charge carrier mobilities, μ, in the range of 0.06–0.92 cm2 V−1 s−1 on Si and of 0.16–0.56 cm2 V−1 s−1 on PEN foil.  相似文献   
2.
Complementary thin-film transistor circuits composed of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS–PEN) and a rylene carboxylic diimide derivative for p- and n-channel thin-film transistors (TFTs) were fabricated on flexible foils. The so-called staggered TFT configuration is used, meaning that the semiconductors layers are deposited last. The work-function of the injecting gold electrodes were modified using several self-assembled monolayers (SAMs). For optimized contacts the mobility of the n- and p-channel TFTs was 0.5 cm2/Vs and 0.2 cm2/Vs, respectively. Strongly degraded performance is obtained when the n-channel material was printed on contacts optimized for the p-channel TFT, and vice versa. This illustrates that for CMOS circuits we need careful work-function engineering to allow proper injection for both electrons and holes. We show for the first time that by using a bimolecular mixture for the SAM we can systematically vary the work function, and demonstrate how this affects the performance of discrete n-type and p-type transistors, as well as CMOS inverters and ring oscillators. Under optimal processing conditions we realized complementary 19-stage ring oscillators with 10 μs stage delay operating at 20 V.  相似文献   
3.
Five different indium‐tin‐oxide free (ITO‐free) polymer solar cell architectures provided by four participating research institutions that all presented a laboratory cell performance sufficient for use in mobile and information and communication technology (ICT) were evaluated based on photovoltaic performance and lifetime tests according to the ISOS protocols. The comparison of the different device architectures was performed using the same active material (P3HT: PCBM) and tested against an ITO‐based reference device. The active area was 1 cm2 and rigid glass or flexible polyester substrates were employed. The performance results were corroborated by use of a round robin methodology between the four participating laboratories (DTU/DK, ECN/NL, Frauenhofer ISE/DE, and the Holst Centre/NL), while the lifetime testing experiments were carried out in only one location (DTU). Five different lifetime testing experiments were carried out for a minimum of 1000 h: (1) shelf life (according to ISOS‐D‐1); (2–3) stability under continuous 1 sun illumination (1000 Wm?2, AM1.5G) at low (37 ± 3°C) and high (80 ± 5°C) temperatures (according to ISOS‐L‐1 and ISOS‐L‐2); (4) stability under continuous low‐light conditions at 0.1 sun (100 Wm?2, AM1.5G, 32°C) (according to ISOS‐LL); (5) continuous illumination (670 Wm?2, AM1.5G) at high temperature (65°C) and high humidity (50% RH) (according to ISOS‐L‐3). Finally, the upscaling compatibility of these device architectures based on the device photovoltaic behavior, stability and scalability were identified and we confirm that an architecture that presents a high score in only one aspect of the solar cell performance is not sufficient to justify an investment in upscaling. Many will require further technical development. © 2013 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 130: 944‐954, 2013  相似文献   
4.
Abstract

To study fouling in steam cracker convection section tubes, accurate tube wall temperature profiles are needed. In this work, tube wall temperature profiles are calculated using a hybrid model, combining a one-dimensional (1D) process gas side model and a computational fluid dynamics (CFD) flue gas side model. The CFD flue gas side model assures the flue gas side accuracy, accounting for local temperatures, while the 1D process gas side model limits the computational cost. Flow separation in the flue gas side at the upper circumference of each tube suggests the need for a compartmentalized 1D approach. A considerable effect is observed. The hybrid CFD-1D model provides accurate tube wall temperature profiles in a reasonable simulation time, a first step towards simulation-based design of more efficient steam cracker convection sections.  相似文献   
5.
6.
由通用交流适配器供电的消费品和PC外设的数量正在迅速增长。该适配器是指能插入频率在47到63Hz间,提供电压有效值在90V至264V范围内的交流电插座上的适配器。这些AC适配器体积小巧且提供连续的超过50W的输出功率,从而使许多设备不再需要内置电源。在打印机等应用中,对峰值功率有较高的要求,它们在短时间的突发工作以外,要有相当长的一段时间  相似文献   
7.
The radiation and convection section of a steam cracker are thermally coupled. Optimization and design requires a coupled simulation of both sections. In this work a 1D model for the convection section, CONVEC‐1D, is developed. Several models for the different heat transfer phenomena are implemented and evaluated. For flow boiling, an empirical and a mechanistic model are developed and compared for both single‐ and multicomponent hydrocarbon feeds. The latter is performing best over a wide range of operating conditions, taking into account the different two‐phase flow regimes. The coupled iterative procedure is demonstrated for an n‐pentane steam cracker convection section.  相似文献   
8.
An upscalable, self‐aligned patterning technique for manufacturing high‐ performance, flexible organic thin‐film transistors is presented. The structures are self‐aligned using a single‐step, multi‐level hot embossing process. In combination with defect‐free anodized aluminum oxide as a gate dielectric, transistors on foil with channel lengths down to 5 μm are realized with high reproducibility. Resulting on‐off ratios of 4 × 106 and mobilities as high as 0.5 cm2 V?1 s?1 are achieved, indicating a stable process with potential to large‐area production with even much smaller structures.  相似文献   
9.
10.
ABSTRACT

This work discusses fouling in the vapor–steam mixture overheater in the convection section of an industrial steam cracker due to the thermal degradation of heavy hydrocarbon droplets deposited on the tube wall. A spray of heavy hydrocarbon multicomponent droplets is injected in a tube of the vapor–steam mixture overheater and the path of the droplets through the tube is followed by an Eulerian–Lagrangian computational fluid dynamics simulation. To study tube fouling, the droplet impingement behavior on the wall, the evaporation of the deposited liquid, and a coking model describing thermal coke formation due to degradation of heavy hydrocarbons are required. To describe the droplet impingement behavior, a regime map for single component millimeter-sized droplets is taken from the literature. Two simulations are performed to study fouling problems in a vapor-mixture overheater tube. Simulation results are found to be grid sensitive. By analyzing and comparing simulation results it is concluded that reliable fouling data require a regime map for the impingement of multicomponent heavy hydrocarbon micron-sized droplets.  相似文献   
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