A comparative study on structural,morphological and photocatalytic properties of anodically grown ZnO nanowires under varying parameters

Journal of Materials Science: Materials in Electronics - In this study, zinc oxide (ZnO) nanowires (NWs) were successfully produced on Zn plates through electrochemical anodization in potassium...     

Optimal Control of the Primary Drying Stage of Freeze Drying of Solutions in Vials Using Variational Calculus

The problem of operating freeze drying of pharmaceutical products in vials placed in trays of a freeze dryer to remove free water (in frozen state) at a minimum time was formulated as an optimal control problem. Two different types of freeze dryer designs were considered. In type I freeze dryer design, upper and lower plate temperatures were controlled together, while in type II freeze dryer design, upper and lower plate temperatures were controlled independently. The heat input to the material being dried and the drying chamber pressure were considered as control variables. Constraints were placed on the system state variables by the melting and scorch temperatures during primary drying stage. Necessary conditions of optimality for the primary drying stage of freeze drying process in vials are derived and presented. Furthermore, an approach for constructing the optimal control policies that would minimize the drying time for the primary drying stage was given. In order to analyze optimal control policy for the primary drying stage of the freeze-drying process in vials, a rigorous multi-dimensional unsteady state mathematical model was used. The theoretical approach presented in this work was applied in the freeze drying of skim milk. Significant reductions in the drying times of primary drying stage of freeze drying process in vials were obtained, as compared to the drying times obtained from conventional operational policies.     

Fundamental properties of reset control systems

Reset controllers are linear controllers that reset some of their states to zero when their input is zero. We are interested in their feedback connection with linear plants, and in this paper we establish fundamental closed-loop properties including stability and asymptotic tracking. This paper considers more general reset structures than previously considered, allowing for higher-order controllers and partial-state resetting. It gives a testable necessary and sufficient condition for quadratic stability and links it to both uniform bounded-input bounded-state stability and steady-state performance. Unlike previous related research, which includes the study of impulsive differential equations, our stability results require no assumptions on the evolution of reset times.     

Characterization of rheological properties of systems containing sugar substitutes and carrageenan

The effects of addition of κ-carrageenan to solutions containing 40% (w/w) sugar substitute on the rheological properties of these systems were investigated at 25 °C using a rotational viscometer at rotational speeds of 6, 12, 30, and 60 rev min⁻¹. The flow behaviour of the solutions was adequately described by the power law model with or without yield stress. The consistency index ( K ) and the flow behaviour index ( n ) were determined from shear stress vs. shear rate data. The flow parameters of the solutions depended on the carrageenan concentration. The apparent viscosities of the systems decreased with increasing shear rate, indicating pseudoplastic behaviour. The final carrageenan concentration was found to be an effective factor controlling the degree of sliminess of the model food systems studied.     

Fast Decodable Turbo Codes

Decoding delay is an important consideration for the use of turbo codes in practical applications. We propose a new structure for turbo codes which is very suitable for parallel decoding. It is shown by union bound analysis and simulation results that the proposed system performance is comparable to that of the classical turbo codes     

A capacitive threshold-logic gate

A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described     

Adoption of Technology-Mediated Distance Education: A longitudinal analysis

We investigated the factors that facilitated the fast adoption and utilization of Technology-Mediated Distance Education (TMDE) among higher education institutions. Our analysis was based on a rich data set on the utilization of TMDE between the 1997–1998 and 2000–2001 academic years. The analysis showed that size, public/private status, and location significantly predicted its actual adoption. Being in an urban location negatively affected enrollment in the courses at the undergraduate but not at the graduate level. While the intent to adopt TMDE correlated significantly with actual adoption, many schools that were not interested in TMDE in 1997–1998 adopted it by 2000–2001. Interestingly, late adopters utilized certain technologies as frequently as early adopters, such as synchronous Internet-based instruction and the use of CD-ROMs.     

Microarchitectures for Managing Chip Revenues under Process Variations

As transistor feature sizes continue to shrink intothe sub-90nm range and beyond, the effects of process variationson critical path delay and chip yields have amplified. A commonconcept to remedy the effects of variation is speed-binning, bywhich chips from a single batch are rated by a discrete range offrequencies and sold at different prices. In this paper, we discussstrategies to modify the number of chips in different bins andhence enhance the profits obtained from them. Particularly, wepropose a scheme that introduces a small Substitute Cacheassociated with each cache way to replicate the data elementsthat will be stored in the high latency lines. Assuming a fixedpricing model, this method increases the revenue by as much as13.8% without any impact on the performance of the chips.