A single chip multi-channel surface plasmon resonance imaging system

A single chip, multi-channel surface plasmon resonance (SPR) imaging system has been developed. The equipment has no moving parts and uses a single sensor chip on which multiple channels can be incorporated. A light emitting diode is used as a photon source while a CCD camera forms the detector. The optical configuration has been designed to achieve a uniform illumination of the sample over a fixed area with a range of incident angles. A calibration test using sucrose solutions shows that the sensitivity of the equipment is 4.3×10⁻⁴ refractive index units per pixel line-pair. The use of the system for simultaneous interrogation of different polyelectrolyte thin films, formed by the electrostatic layer-by-layer deposition method, is demonstrated. A reversible pH-dependent response for these organic layers is also reported.     

Fibrosis of Peritoneal Membrane as Target of New Therapies in Peritoneal Dialysis

Peritoneal dialysis (PD) is an efficient renal replacement therapy for patients with end-stage renal disease. Even if it ensures an outcome equivalent to hemodialysis and a better quality of life, in the long-term, PD is associated with the development of peritoneal fibrosis and the consequents patient morbidity and PD technique failure. This unfavorable effect is mostly due to the bio-incompatibility of PD solution (mainly based on high glucose concentration). In the present review, we described the mechanisms and the signaling pathway that governs peritoneal fibrosis, epithelial to mesenchymal transition of mesothelial cells, and angiogenesis. Lastly, we summarize the present and future strategies for developing more biocompatible PD solutions.     

Gain-compensated sample-and-hold circuit for high frequency application

A novel and fast and accurate sample-and-hold circuit is presented which can be designed using conventional single stage amplifiers. The offset contribution to the output voltage is intrinsically compensated and the clock-feedthrough error can be reduced by slightly changing the clock phase scheme.<>     

An Overview of Analog Feedback Part II: Amplifier Configurations in Generic Device Technologies

In this second installment of a two part paper that overviews analog feedback circuits, computationally efficient and general feedback analysis techniques applicable to virtually all three and four terminal device technologies are formulated. As developed in Part I, these techniques coalesce signal flow and two port network theories in a way that clearly illuminates the loop gain, driving point I/O impedances, and other characteristics of any type of feedback configuration. More than simply developing the signal flow-two port methodology, this paper demonstrates its design-oriented utility by applying the new technique to the problem of assessing the performance attributes and limitations of four single loop and two dual loop feedback architectures.Three advantages are gleaned by the signal flow-two port method of feedback network analysis. The first advantage is its amenability to a straightforward application of the stability theories and compensation strategies discussed in Part I. The second is its ability to underscore the magnitude of potentially troublesome feedforward factors associated with the feedback network. Once the extent of this parasitic feedforward is highlighted, the topological nature of appropriate feedforward compensation is relatively easy to innovate. The third advantage of signal flow-two port analytical methods is its ability to simplify the analysis of dual loop feedback architectures. This last advantage is noteworthy in view of the fact that dual feedback loops offer the only practical analog mechanism for desensitizing the gain and I/O impedances with respect to uncertainties in open loop parameters.     

Filtering for bimodal systems: the case of unknown switching statistics

This paper considers the problem of state estimation for discrete-time systems whose dynamics randomly switches between two linear stochastic behaviors (bimodal systems). The novelty of this paper is that no statistical information on the switching process is assumed available for the filter design. Two different approaches are here proposed to solve the estimation problem in these conditions. One method is based on a combined use of stochastic singular systems and of the minimax filtering theory, while the other relies on the maximum entropy principle. Based on these approaches two filtering algorithms are derived, whose features are theoretically and numerically compared. Some attention has been devoted to the study of the asymptotic properties of both the filters.     

Propagation Delay of an RC-Chain With a Ramp Input

In this brief, two simple semi-analytical models which allow the estimation of the propagation delay of an RC-chain with a linear input are presented. The closed-form models can be used to evaluate the propagation delay of wires in modern VLSI and ULSI processes. The two approximations, a continuous function and a piecewise function, exhibit a maximum error lower than 15% at the end of the chain. The models have been validated extensively through circuit simulations. In particular, 1000 different RC-chains have been considered and simulated demonstrating the accuracy of the proposed models with respect to the most widely used Elmore delay metric     

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications     

A novel approach to characterization of progressive breakdown in high-k/metal gate stacks

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO₂/interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported.     

1 V CMOS output stage with excellent linearity

A CMOS low-voltage output stage based on a push-pull topology is proposed. It is driven by a differential signal and its symmetric topology provides excellent intrinsic linearity. It can work with a power supply as low as 1 V and when loaded with a 500 /spl Omega/ resistor it exhibits negligible even harmonic components whilst odd components are maintained well below -20 dB up to 900 mV/sub pp/ of the output signal. Moreover, the output stage includes a simple current control which accurately sets the bias condition.