LPNN-based approach for LASSO problem via a sequence of regularized minimizations

In compressive sampling theory, the least absolute shrinkage and selection operator (LASSO) is a representative problem. Nevertheless, the non-differentiable constraint impedes the use of Lagrange programming neural networks (LPNNs). We present in this article the -LPNN model, a novel algorithm that tackles the LASSO minimization together with the underlying theory support. First, we design a sequence of smooth constrained optimization problems, by introducing a convenient differentiable approximation to the non-differentiable -norm constraint. Next, we prove that the optimal solutions of the regularized intermediate problems converge to the optimal sparse signal for the LASSO. Then, for every regularized problem from the sequence, the -LPNN dynamic model is derived, and the asymptotic stability of its equilibrium state is established as well. Finally, numerical simulations are carried out to compare the performance of the proposed -LPNN algorithm with both the LASSO-LPNN model and a standard digital method.     

Hot carrier reliability of RF N- LDMOS for S Band radar application

This paper presents an innovative reliability bench specifically dedicated to high RF power device lifetime tests under pulse conditions for radar application. A base-station dedicated LDMOS transistor has been chosen for RF lifetests and a complete device electric characterization has been performed. A whole review of its critical electrical parameters after accelerated ageing tests is proposed and discussed. This study tend to explain the physical degradation mechanisms occurred during RF life-tests by means of 2D ATLAS-SILVACO simulations. Finally, the paper demonstrates that N-LDMOS degradation is linked to hot carriers generated interface states (traps) and trapped electrons, which results in a build up of negative charge at Si/SiO2 interface. More interface states are created at low temperature due to a located maximum impact ionization rate at the gate edge.     

Comparative analysis of RF LDMOS capacitance reliability under accelerated ageing tests

This paper presents the results of comparative reliability study of C–V characteristics through three accelerated ageing tests for stress applied to an RF LDMOS: Thermal shock tests (TST, air–air test), thermal cycling tests (TCT, air–air test) and high temperature storage life (HTSL). The two first tests are carried out with a drain current flowing through the device during stress. The investigation findings of electrical parameter degradations after various ageing tests are discussed. Feedback capacitance (Crs) is reduced by 16% and gate–drain capacitance (Cgd) by 42%. This means that the tracking of these parameters enables to consider the hot carrier injection as the dominant degradation phenomenon. A physical simulation software has been used to confirm qualitatively degradation phenomena.     

Automatic speech recognition system for Tunisian dialect

Although Modern Standard Arabic is taught in schools and used in written communication and TV/radio broadcasts, all informal communication is typically carried out in dialectal Arabic. In this work, we focus on the design of speech tools and resources required for the development of an Automatic Speech Recognition system for the Tunisian dialect. The development of such a system faces the challenges of the lack of annotated resources and tools, apart from the lack of standardization at all linguistic levels (phonological, morphological, syntactic and lexical) together with the mispronunciation dictionary needed for ASR development. In this paper, we present a historical overview of the Tunisian dialect and its linguistic characteristics. We also describe and evaluate our rule-based phonetic tool. Next, we go deeper into the details of Tunisian dialect corpus creation. This corpus is finally approved and used to build the first ASR system for Tunisian dialect with a Word Error Rate of 22.6%.     

A 5000 h RF life test on 330 W RF-LDMOS transistors for radars applications

A reliability test bench dedicated to RF power devices is used to improve 330 W LDMOS in a radar conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. Numerous duty cycles are applied in order to stress LDMOS. It shows with tracking all this parameters that only few hot carrier injection phenomenon appear with no incidence on RF figures of merit (P_out or PAE). Robustness and ruggedness are shown for LDMOS with this bench for radar applications in L-band.     

Long-time anodisation of titanium in sulphuric acid

The long-time behaviour of CP titanium in 1 M H₂SO₄ has been investigated. The authors revealed electrochemical behaviour during the long-time chrono-amperometric experiments. The ex-situ observations (EIS, ellipsometry, SEM and optical microscopy) brought out information concerning morphological changes of the surface as well as the change in the oxide thickness during the anodic oxidation process. From the obtained data, the authors developed a hypothesis describing the potentiostatic anodisation of titanium at voltages (up to 15 V) in 1 M H₂SO₄ with respect to time of anodisation.     

New pulse mode neuro-fuzzy hardware architecture and application to image denoising

This paper focuses on a new digital architecture of pulse mode neuro-fuzzy system (PMNFS) with on-chip learning ability. The main purpose goal is to make use of the outstanding features of neuro-fuzzy in function approximation, and implement a reconfigurable architecture with on-chip learning on a field-programmable gate array (FPGA) platform. Details of the whole design with on-chip learning solutions are given. As an application illustrating the efficiency and scalability of the proposed PMNFS, we have considered the approximation of image denoising, which is a very important step in image processing. Experimental results show great efficiency of the proposed method, outperforming other denoising techniques. It was also demonstrated that such a system is strongly adaptive and gives good restored images independently of the kind of noises. Owing to learning, such feature cannot be met with conventional denoising techniques. Design synthesis results on a virtex II PRO FPGA platform are presented. Comparisons with conventional techniques as well as neural ones show higher performances of the designed PMNFS.     

A bipolar implementation of the Beta neuron

The great flexibility of the Beta function and its universal approximation characteristics, make Beta basis function neural networks (BBFNNs) very useful. We present a hardware implementation of the Beta neuron. The proposed circuit was designed by using a standard bipolar technology. PSPICE simulations show the good concordance of the output of our circuit with the analytic Beta function. We also successfully integrated the electronic Beta neuron in the design of a BBFNN that approximates a nonlinear mapping.     

A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard

High-efficiency video coding is the latest standardization effort of the International Organization for Standardization and the International Telecommunication Union. This new standard adopts an exhaustive algorithm of decision based on a recursive quad-tree structured coding unit, prediction unit, and transform unit. Consequently, an important coding efficiency may be achieved. However, a significant computational complexity is resulted. To speed up the encoding process, efficient algorithms based on fast mode decision and optimized motion estimation were adopted in this paper. The aim was to reduce the complexity of the motion estimation algorithm by modifying its search pattern. Then, it was combined with a new fast mode decision algorithm to further improve the coding efficiency. Experimental results show a significant speedup in terms of encoding time and bit-rate saving with tolerable quality degradation. In fact, the proposed algorithm permits a main reduction that can reach up to 75 % in encoding time. This improvement is accompanied with an average PSNR loss of 0.12 dB and a decrease by 0.5 % in terms of bit-rate.     

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding

Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required to achieve real-time compression performance. Many fast search block matching motion estimation (BMME) algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose three new hardware architectures of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. These architectures use pipeline and parallel processing techniques and present minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit for the three proposed architectures.