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1.
Kuo  Shu-Chun  Chien  Tsair-Wei  Chou  Willy 《Scientometrics》2022,127(2):1191-1194
Scientometrics - The article published on 5 July 2021 is well-written and of interest. However, some improvements could be made, such as ten Tables/Figures can be shortened to highlight the focused...  相似文献   
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International Journal of Control, Automation and Systems - In this paper, a composite fault-tolerant control problem is studied for a class of uncertain nonlinear system with asymmetric input...  相似文献   
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Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.  相似文献   
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实验考察了胜利孤东稠油井下催化水热裂解和乳化/催化水热裂解降黏效果。所用催化剂为水溶性铁镍钒体系,Fe3+∶Ni2+∶VO4+=5∶1∶1,100 g稠油与30 g 0.5%催化剂水溶液在240℃反应24小时。原始黏度(50℃)11.0和8.36 Pa.s的两种稠油裂解并静置除水后,黏度降低76.2%和75.6%,室温放置60天后降黏率下降小于3个百分点,气相色谱显示裂解后轻组分明显增加,红外光谱显示稠油组分发生脱羧反应且芳环数减少。讨论了稠油催化水热裂解反应机理。所用化学助剂JN-A在油水中均可溶,耐温达250℃,耐矿化度达50 g/L,其水溶液以30∶100的质量比与稠油混合时形成低黏度的O/W乳状液。当水相含1.0%JN-A和0.5%催化剂时,两种稠油水热裂解后的反应混合物为O/W乳状液,黏度仅为319和309 mPa.s,静置除水后的稠油降黏率增加到86.5%和87.3%,其中的轻组分含量进一步增加。该井下乳化/催化水热裂解复合降黏法成功地用于孤东两口蒸汽吞吐井,稠油井作业后初期采出的原油黏度由~9 Pa.s降低到1 Pa.s左右,随采油时间延长而逐渐升高,约50天后超过4Pa.s。图2表6参5。  相似文献   
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The Synthesis of Sulfated Titanium Oxide Nanotubes   总被引:1,自引:0,他引:1  
TiO2 nanotubes can be prepared in gram quantities by treating anatase TiO2 powder with concentrated NaOH solution. These TiO2 nanotubes acquired strong acidity after being impregnated with sulfuric acid solution and calcined at 300 °C. The anatase TiO2 powder used to prepare the nanotube did not catalyze the esterification between cyclohexanol and acetic acid, while sulfated TiO2 nanotubes were very reactive toward the esterification reaction.  相似文献   
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The solid-state phase transitions in ammonium nitrate (AN)-potassium nitrate (KN) system, and the equilibrium AN-KN phase diagram have been determined by using differential scanning calorimetry and high-temperature in situ x-ray diffractometry. Sample preparation was performed in a special “dry room” with very low humidity. A single phase region (AN III) with no phase transitions to 373 K was observed in the composition range 5 to 20% KN; this is critical for use in air bag gas generators. The high-temperature KN phase (KN I) has a wide range of stability from 20 to 100 wt.% KN. There are one eutectic, two eutectoid, three peritectoid, and one congruent transformations in this phase diagram. Two new nonstoichiometric phases were found at lower temperatures in the mid-composition range between the AN and KN terminal solid solutions. Details of the phase equilibria are presented.  相似文献   
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An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters  相似文献   
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