外部高速缓存与非易失内存结合的混合内存体系结构特性评测

以非易失性存储器(NVM)作为主存且以动态随机存取存储器(DRAM)作为片外高速缓存(EC),是一种可以满足大数据应用内存容量需求的新型混合内存结构(EC-NVM).该结构同时具有NVM的大存储容量和DRAM的低存取延迟的优点.传统的结构是以片内SRAM作为片内高速缓存(IC)且以DRAM作为主存(IC-DRAM).与...     

一种基于Trace精度改进的内存系统模拟器优化方法

随着计算机系统规模的不断增长,计算机系统结构的研究对于如何更有效地利用各个部件的性能显得尤为重要.但是在系统结构的研究中,由于研究对象规模过大,采用模拟器进行模拟测试是一种常用的方法.但是在使用全系统模拟器的时候,将整个系统进行模拟会造成实验效率的降低和模拟器程序的维护困难.因此,使用基于trace输入的模拟器成为了一种提高模拟器效率的常用方法,但是由于trace不能良好地表现计算机系统某些部分的运行特性,难以避免地存在一定的模拟误差.对此,提出了一种基于trace精度改进的内存系统模拟器优化方法,通过增加trace中包含的内容、提高trace的精度并在内存系统模拟器中实现相应的支持机制,从而在不影响模拟器运行效率的情况下提高内存系统模拟器的运行精度.     

MIMS: Towards a Message Interface Based Memory System

The decades-old synchronous memory bus interface has restricted many innovations in the memory system, which is facing various challenges （or walls） in the era of multi-core and big data. In this paper, we argue that a message- based interface should be adopted to replace the traditional bus-based interface in the memory system. A novel message interface based memory system called MIMS is proposed. The key innovation of MIMS is that processors communicate with the memory system through a universal and flexible message packet interface. Each message packet is allowed to encapsulate multiple memory requests （or commands） and additional semantic information. The memory system is more intelligent and active by equipping with a local buffer scheduler, which is responsible for processing packets, scheduling memory requests, preparing responses, and executing specific commands with the help of semantic information. Under the MIMS framework, many previous innovations on memory architecture as well as new optimization opportunities such as address compression and continuous requests combination can be naturally incorporated. The experimental results on a 16-core cycle-detailed simulation system show that： with accurate granularity message, MIMS can improve system performance by 53.21% and reduce energy delay product （EDP） by 55.90%. Furthermore, it can improve effective bandwidth utilization by 62.42% and reduce memory access latency by 51% on average.     

一种多线程程序内存系统模拟器Trace驱动仿真方法

伴随大数据计算时代的到来,片上多核处理器为提高多线程程序服务器吞吐率发挥巨大作用,同时其内存系统的访问延迟越来越影响系统性能.目前,路径驱动(trace-driven)仿真方法比执行驱动(execution-driven)运行速度快,被内存系统研究者广泛采用.但是路径驱动在仿真并发线程时,会同时导致宏观和微观的访存错位.而实际多线程程序运行过程中,不会发生这种访存错位行为.通过理论分析和计算,访存错位引起路径驱动的仿真结果存在明显偏差.针对上述问题,提出了一种方法来避免路径驱动仿真发生宏观和微观访存错位,精确回放采集阶段的多线程程序行为.实验数据显示,在避免宏观访存trace错位后,多线程程序的多个仿真指标出现最高10.22％的变化;对于部分访存密集型的多线程程序,避免微观访存trace错位可以使算数平均IPC出现大于50％的变化.为研究交互线程的内存系统行为提供一种更加准确的路径驱动方法.