嵌入式单精度扩展浮点RISC微处理器的设计

文章介绍了一种单精度浮点RISC微处理器的核心设计思想，改进设计了一种新颖的芯片内置总线仲裁器控制总线、中断处理机管理中断、数据中继器操作存储器。采用三阶布斯算法和浮点并行算法设计FALU和FMUL，并设计了嵌入式128KSRAM，最后用UMC0．25μmCMOS工艺库进行综合、布局布线完成版图设计。版图后模拟验证以及CPLD硬件仿真验证表明：微处理器工作主频达到50MHz，全部共88条指令运行正常。     

一种基于格雷码的电路自测试序列分配算法

为了降低组合电路内建自测试的测试功耗,提出了一种基于格雷码的测试序列分配算法.分组式格雷码序列和种子序列相异或生成单跳变测试序列,根据电路的基本输入权重,合理分配测试序列位,减少了电路内部节点的跳变,有效降低了电路的测试功耗.该算法应用在改进的布斯二阶乘法器的自测试中,根据不同的数据通道位宽,相对于传统自测试架构,测试...     

Power-optimal encoding for low-power address bus

This paper presented a novel bus encoding method to reduce the switching activity on address buses and hence reduce power dissipation. Dynamic-sorting encoding(DSE) method reduces the power dissipation of address bus based on the dynamic reordering of the modified offset address bus lines. This method reorders the ten least significant bits of offset address according to the range of offset address, and the optimal sorting pattern is transmitted through the high bits of address bus without the need for redundant bus lines. The experimental results by using an instruction set simulator and SPEC2000 benchmarks show that DSE method can reduce signal transitions on the address bus by 88.2%, and the actual overhead of the encoder circuit is estimated after encoder is designed and synthesized in 0.18-μm CMOS technology. The results show that DSE method outperforms the low-power encoding schemes presented in the past.     

基于非冗余排序的地址总线的功耗优化编码

提出了一种新的低功耗非冗余排序总线编码方法．通过对改进的偏移地址线的动态重排以降低具有高负载的地址总线的功耗．该编码方法根据偏移地址的值域对地址总线的低位进行优化重排，通过高位地址总线传送排序矢量至存储器的地址接收端．相对于传统的地址总线编码方法，具有更低的总线跳变率．实验结果表明。采用所提出的非冗余排序总线编码．地址总线的跳变率降低了88．2％，功耗减少了76．1％．有效降低了地址总线的功耗．