Synthesizing Energy-Efficient Embedded Systems with LOPOCOS

In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimizationsteps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.     

Investigating the effect of varying block size on power and energy consumption of GPU kernels

The Journal of Supercomputing - Power consumption is likely to remain a significant concern for exascale performance in the foreseeable future. In addition, graphics processing units (GPUs) have...     

Simultaneous scheduling, allocation and binding in high levelsynthesis

The authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding in high level synthesis (HLS). Globally optimum data path realisations with efficient single-level interconnect structures are rapidly obtained using a novel strategy for the generation of new synthesis solutions applied to simulated annealing. An example of a fifth-order wave digital filter is included     

Current mode filter structure based on dual output transconductanceamplifiers

A new current-mode filter structure based on the dual output operational transconductance amplifier is described. By appropriate choice of components, the structure provides lowpass, highpass and bandpass responses. Experimental results which confirm the theoretical analysis are given     

Dynamics-based amplification of RNA function and its characterization by using NMR spectroscopy

The ever-increasing cellular roles ascribed to RNA raise fundamental questions regarding how a biopolymer composed of only four chemically similar building-block nucleotides achieves such functional diversity. Here, I discuss how RNA achieves added mechanistic and chemical complexity by undergoing highly controlled conformational changes in response to a variety of cellular signals. I examine pathways for achieving selectivity in these conformational changes that rely to different extents on the structure and dynamics of RNA. Finally, I review solution-state NMR techniques that can be used to characterize RNA structural dynamics and its relationship to function.     

Synchronization overhead in SOC compressed test

Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-chip. This paper analyzes the sources of synchronization overhead and discusses the different tradeoffs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.     

New high-order filter structures using only single-ended-input OTAs and grounded capacitors

Despite the wealth of literature on operational transconductance amplifier (OTA)-C filters, the synthesis of high-order filter characteristics is still an active topic. In this paper the realization of voltage transfer functions based on canonical current-mode follow-the-leader-feedback (FLF) OTA-C structures are investigated. Two new structures are presented, which use only single-ended-input OTAs and grounded capacitors. The first structure has a single voltage input and multiple voltage outputs taken from different nodes, which enables it to provide simultaneous outputs of different filter functions. The second structure has a single voltage output and single voltage input distributed to different circuit nodes for a universal realization. The authors not only propose such filter structures, but also show how analytical synthesis can be used to produce filter circuits that have less active elements than those recently reported voltage-mode structures which are based on differential-input OTAs. This represents another attractive feature from chip area, and power consumption point of view. Simulation results verifying the theoretical analysis of the proposed filter structure are included.     

Current-mode elliptic filter design based on symmetrical current switching

This paper describes a current-mode elliptic filter structure based on dual-output OTAs and grounded capacitors. The filter is capable of producing both lowpass and highpass notch responses without changing the filter structure. This is achieved using a symmetrical current switching technique based on two switches controlled with a 2-bit digital word. The proposed filter structure forms a basic second-order building block in the design of high-order elliptic filters with tuneable frequency response. To confirm the theoretical analysis, simulated and measured results of fourth-order elliptic lowpass and highpass filters with tuneable bandwidth in the range of 0.65MHz to 1.3MHz are included. Finally, detailed analysis of the OTAs non-ideal parameters on the filter performance is presented and an example is given.