ESD: a pervasive reliability concern for IC technologies

Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed     

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I -V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T_i to 3T_i , where T_i is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T_i is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed     

Photon emission as a tool for esd failure localization and as a technique for studying ESD phenomena

Photon emission microscopy gives the opportunity for non-destructive localization of failure sites on VLSI chips. Failures that can be detected using photon emission microscopy are gate-oxide breakdown, latch-up, junction breakdown and intermetal oxide failures. This makes it a valuable evaluation technique of failures in ESD protection circuits. Real-time photon emission observations of reverse-biased transistors showed that this technique is also an important tool in the evaluation and development of ESD protection circuits.     

ESD in integrated circuits

A review of the effects of electrostatic discharge (ESD) on semiconductor integrated circuits is presented. The principles of the human body model (HBM), the machine model (MM) and the charged device model (CDM) test methods are outlined, and their relative merits and drawbacks are discussed. Techniques, such as the transmission line pulse method, which may be used to characterise ESD protection circuit elements are also presented. The concept of ESD protection circuit designs and some typical ESD protection circuit elements are presented. The main design and process parameters are identified, and the main categories of damage under ESD conditions are shown. Models of the behaviour of the protection circuit elements under high current conditions are presented, and the boundary conditions for damage are discussed. The issues that will influence ESD protection circuit behaviour in the future are discussed.     

ESD issues for advanced CMOS technologies

As technologies advance towards the deep submicron, the ESD protection design issues have been known to become more critical. This paper examines the recent trends in ESD protection designs, the technology impact, and the specific approaches to build-in ESD reliability. It is shown that the efficient performance of advanced protection designs requires an optimized process that can meet the ESD robustness criterion.     

The Changing Design Landscape

This sidebar explains that the burden of enabling Moore's law to continue is gradually moving from the process technologists to the designers. As technology moves from 65 nm to 22 nm, the number of transistors on a big chip will go from approximately 2 billion to 15 billion. Technology scaling and the manufacturing process come with higher variations in transistors both locally and globally on a chip. Moreover, the large number of components on a single chip will lead to reliability, aging, and defect limitations that could no longer be eliminated through margins or overdesign. They must be detected and compensated without affecting the performance goals of the chip. The research direction of the GSRC is aimed at solutions to these obstacles, for the continued advancement of system performance needs.     

High-current failure model for VLSI interconnects under short-pulsestress conditions

Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 μm CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects     

Electrostatic pulse breakdown in nmos devices

The electrostatic discharge (ESD) sensitivity of small dimension n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) has been investigated. NMOS FETs of varying dimensions and a constant gate oxide thickness of 400® were each subjected to a single ESD voltage pulse of between 50 and 250V at temperatures between 25 and 200°C. Over 4000 devices were used, all resident on a single 3 inch silicon wafer. The object of the experiment was to determine the dependence of device ESD sensitivity on temperature, voltage and device dimensions as well as to investigate the mechanisms that cause oxide breakdown as a result of ESD damage. No temperature dependence of device ESD sensitivity was observed within the range of the experiment. A significant voltage dependence was observed, with degradation accounting for over 80 per cent of devices at 250V. A cumulative ESD effect was observed, whereby the degradation of device performance was found to increase with the number of applied pulses. Analysis of the breakdown characteristics revealed that the cause of damage was oxide breakdown. Application of the ESD pulse appears to lead to oxide breakdown through impact ionization within the oxide, the very short duration of the pulse not being favourable to processes involving electron trapping unless these traps are already present in the oxide.