Low power and high speed design issues of CMOS Hamming code generation and error detection circuit at 22 nm and 16 nm channel length of MOS transistor

Microsystem Technologies - This paper represents low power and high speed design issues of Hamming code generation and error detection circuit using complementary metal oxide semiconductor (CMOS)...     

Preface

Microsystem Technologies -     

Favorable influence of ssDNA-functionalized SWCNT on the navigation pattern of C. elegans

Microsystem Technologies - Single-Walled Carbon Nanotubes (SWCNTs) are widely used as potential carriers in drug delivery systems. The objective of this work was to observe the effects of pristine,...     

Metal to semimetal conversion by band structure engineering of SWCNT by DNA nucleobase functionalization

Microsystem Technologies - Pristine metallic single-walled carbon nanotubes (6, 0), surface engineered with pyrimidine type DNA nucleobases, thymine and cytosine respectively, are transformed into...     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

Quantum Analytical Model for Lateral Dual Gate UTBB SOI MOSFET for Analog/RF Performance

Silicon - This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field...     

Effect of high-K dielectric on differential conductance and transconductance of ID-DG MOSFET following Ortiz-Conde model

Microsystem Technologies - Differential conductance and transconductance of double-gate MOSFET are analytically computed in presence of high-K dielectric following Ortiz-Conde model....     

Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs

Microsystem Technologies - The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of...     

Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

A two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor (CNTFET) using coupled mode space approach. Schrödinger and Poisson’s equations are self-consistently solved involving Non-Equilibrium Green’s Function (NEGF) formalism under the ballistic limit along with dissipative effects in terms of self-energy at both the source and drain ends. Effect of structural parameters on drain current, channel length modulation parameter, quantum capacitance, transconductance, subthreshold swing (SS) and drain induced barrier lowering (DIBL) are studied assuming occupancy of only a few lower sub-bands, where comparison is performed taking all other factors, biases and dimensions identical. High-k dielectric (HfO₂) independently surrounding the quantum wire (GaAs) and carbon nanotube shows higher drain current and transconductance for GAAQWT but lower quantum capacitance than that obtained for CNTFET. A smaller variation of CLM for CNFET speaks in favour of it for digital quantum circuit applications, whereas GAAQWT is suitable candidate for low-power applications. Effect of structural parameters is investigated within fabrication limit to analyse the effect on electrical characteristics under lower biasing ranges.     

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gauss's law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g _m/I _d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g _m/I _d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.