Realistic built-in self-test for static RAMs

The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM     

Implementing macro test in silicon compiler design

A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vector storage. The overhead from adding testability is only 10% of the total area and test-program generation is done with 100% fault coverage in a very short time, since there is no need for global test-pattern generation. A set of tools that guide the testability implementation from design to the final test program is described     

Design of Smearing Filters for Data Transmission Systems

In this paper, we introduce a new approach to design smearing and desmearing filters for data transmission systems to suppress pulse-like disturbances inserted in the communication channel. Our method is based on time domain considerations. It consists of the optimization of two merit factors defined for the impulse response functions of the filters. The first one is a measure of the smearing efficiency, and the second one is a measure of the amount of intersymbol interference caused by the insertion of the two filters in the transmission system. Our method will be applied to smearing and desmearing filters for baseband signals as well as for passband signals. In particular, we show that our method leads to filters having a better smearing efficiency and a simpler implementation than the filters obtained by the classical frequency domain approach.     

Macro Testing: Unifying IC And Board Test

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.