Simultaneous determination of granisetron and its 7-hydroxy metabolite in human plasma by reversed-phase high-performance liquid chromatography utilizing fluorescence and electrochemical detection

A highly sensitive and selective high-performance liquid chromatographic method was developed for the determination of granisetron and its active metabolite, 7-hydroxygranisetron (7OH-G) in human plasma. Granisetron is a selective 5-hydroxytryptamine receptor antagonist used in the treatment of cytotoxic drug-induced emesis. The method involves isolation of granisetron, 7OH-G and the internal standards from plasma by solid-phase extraction prior to reversed-phase ion-pair chromatographic separation on an octyl silica column with subsequent quantification of analytes simultaneously either with electrochemical (7OH-G) or fluorescence (granisetron) detectors which are placed in series. The recovery of granisetron and 7OH-G from human plasma was quantitative. Using 1 ml of plasma, the limits of quantification for granisetron and 7OH-G were 0.1 and 0.25 ng/ml, respectively. Linear responses in analyte/internal standard peak-area ratios were observed for analyte concentrations ranging from 0.1 to 50 ng/ml plasma. Precision and accuracy were within 13% across the calibration range for both granisetron and 7OH-G. The method was sufficiently sensitive, accurate and precise to support pharmacokinetic studies for granisetron and 7OH-G, in both normal and patient populations.     

Resource deadlocks and performance of wormhole multicast routingalgorithms

We show that deadlocks due to dependencies on consumption channels are a fundamental problem in wormhole multicast routing. This type of resource deadlocks has not been addressed in many previously proposed wormhole multicast algorithms. We also show that deadlocks on consumption channels can be avoided by using multiple classes of consumption channels and restricting the use of consumption channels by multicast messages. We provide upper bounds for the number of consumption channels required to avoid deadlocks. In addition, we present a new multicast routing algorithm, column-path, which is based on the well-known dimension-order routing used in many multicomputers and multiprocessors. Therefore, this algorithm could be implemented in existing multicomputers with simple changes to the hardware. Using simulations, we compare the performance of the proposed column-path algorithm with the previously proposed Hamiltonian-path-based multipath and an e-cube-based multicast routing algorithms. Our results show that for multicast traffic, the column-path routing offers higher throughputs, while the multipath algorithm offers lower message latencies. Another result of our study is that the commonly implemented simplistic scheme of sending one copy of a multicast message to each of its destinations exhibits good performance provided the number of destinations is small     

Data Architectures for RFID Transactions

We focus on the data models for storing the data generated by radio frequency identification (RFID) transactions and architectures for processing such data. We consider the supply chain comprised of the manufacturer, distributor, retailer, and the consumer. We discuss details of the data generated by RFID transactions and data models to store such data. Different organizations in the supply chain may use this data for different applications such as automatic product ordering, shelf replenishment, and product recall. We present models to anticipate the data requirements generated by RFID transactions and indicate how existing enterprise applications can be adapted to handle RFID data. The results presented in this paper will help a practitioner to 1) design and develop databases and applications for handling RFID data and 2) significantly reduce the storage requirements of RFID data. Using the data architectures, we discuss two supply chain applications-product recall and shelf replenishment-in detail. We present analytical models for the cost and time required for shelf replenishment in a retail store.     

Transistor-level optimization of digital designs with flex cells

The flex-cell approach, either alone or in combination with standard cells, provides an optimally tuned set of building blocks for integrated circuit design when optimality is measured using accepted and quantifiably definable metrics such as clock speed, die size, and power consumption.     

Overlapped Carrier-Sense Multiple Access (OCSMA) in Wireless Ad Hoc Networks

In wireless ad hoc networks (WANets), multihop routing may result in a radio knowing the content of transmissions of nearby radios. This knowledge can be used to improve spatial reuse in the network, thereby enhancing network throughput. Consider two radios, Alice and Bob, that are neighbors in a WANet not employing spread-spectrum multiple access. Suppose that Alice transmits a packet to Bob for which Bob is not the final destination. Later, Bob forwards that packet on to the destination. Any transmission by Bob not intended for Alice usually causes interference that prevents Alice from receiving a packet from any of her neighbors. However, if Bob is transmitting a packet that he previously received from Alice, then Alice knows the content of the interfering packet, and this knowledge can allow Alice to receive a packet from one of her neighbors during Bob's transmission. In this paper, we develop overlapped transmission techniques based on this idea and analyze several factors affecting their performance. We then develop a MAC protocol based on the IEEE 802.11 standard to support overlapped transmission in a WANet. The resulting overlapped CSMA (OCSMA) protocol improves spatial reuse and end-to-end throughput in several scenarios.     

在无线基站中使用FPGA和DSP混合方案提高性价比和灵活性

对无线系统设计人员而言，FPGA和DSP之间的“智能划分”是特性和成本效益的最佳组合。目前还没有适合所有应用的设计方案。DSP和FPGA混合工作是今后非常有希望的解决方案，具有低成本优势，并且没有风险。在无线基站中，系统划分结合了可编程逻辑和DSP，推动了设计实现，有助于产品在市场上获得成功。     

Regulation of ornithine decarboxylase gene expression by the Wilms' tumor suppressor WT1

The importance of ornithine decarboxylase (ODC) to cell proliferation is underscored by the complex array of cell-specific mechanisms invoked to regulate its synthesis and activity. Misregulation of ODC has severe negative consequences on normal cell function, including the acquisition of tumorigenic growth properties by cells overexpressing ODC. We hypothesize that ODC gene expression is a candidate target for the anti-proliferative function of certain tumor suppressors. Here we show that the Wilms' tumor suppressor WT1 binds to multiple sites within the human ODC promoter, as determined by DNase I protection and methylation interference assays. The expression of WT1 in transfected HCT 116, NIH/3T3 and HepG2 cells represses activity of the ODC promoter controlling expression of a luciferase reporter gene. In contrast WT1 expression enhances ODC promoter activity in SV40-transfected HepG2 cells. Both the extent of modulation of ODC gene expression and the mediating WT1 binding elements are cell specific. Constructs expressing WT1 deletion mutants implicate two regions required for repressor function, as well as an intrinsic activation domain. Understanding the regulation of ODC gene expression by WT1 may provide valuable insights into the roles of both WT1 and ODC in development and tumorigenesis.     

Low‐Power and Low‐Hardware Bit‐Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit‐parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application‐specific integrated circuit and field‐programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.     

Models for Cost-Benefit Analysis of RFID Implementations in Retail Stores

In this paper, we focus on the models for analyzing radio frequency identification (RFID) implementations in terms of their costs and benefits. We consider the supply chain comprised of the manufacturer, distributor, retailer, and the consumer. We classify the transactions generated by different RFID tag reads and discuss implementations of the data networks connecting the tag readers at the retail store. Our models consider the cost of implementations including the cost of tag readers, the communication network cost and other infrastructure costs. The analytical models we propose consider the benefits of these implementations including automatic checkout at retail stores and reduced inventory costs due to efficient shelf replenishment.     

简化OEM厂商产品开发流程——FPGA加速WiMAX设计

采用FPGA的WiMAX系统设计 如同Altera的StratixⅡ平台这类具有高效能的FPGA一样,包含了嵌入式的DSP模块、TriMatrix存储器架构、创新的逻辑结构与高速的界面,提供了强大并具集成性的平台来实现WiMAX这类的宽带无线系统.