Analog-to-digital converter based on single-electron tunneling transistors

A novel single-electron tunneling transistors (SETTs) based analog-to-digital converter (ADC) is proposed in this paper. The scheme we propose fully utilizes Coulomb oscillation effect, can properly operate at T>0 K, and only a capacitive divider (built with 2n-2 capacitors) and n pairs of complementary SETTs are required for an n-bit ADC implementation. When compared with other state-of-the-art SET based ADCs our method provides the most compact solution measured in terms of circuit elements and has a potential advantage in terms of conversion speed. To illustrate the operation of the proposed scheme, a 4-bit ADC is demonstrated at 10K by means of simulation.     

An Analysis of Internal Parameter Variations Effects on Nanoscaled Gates

The predicted deterioration of the component quality, due to the shrinking of components to near atomic scale, threatens the effectiveness and the applicability of conventional digital system design methodologies in the giga and tera-scale integration era. Three aggression sources support the previous statement: i) the increasing device parameter variability induced by the extreme reduction of the critical feature sizes and the intrinsic nature of new devices; ii) the intense and practically unpredictable internal noise; and iii) the large number of physical defects. This paper provides a detailed analysis of the noise and parameter variations effects on a basic processing gate. We derive formulas to calculate the expected value and the variance of the gate output under the effects of noise, threshold, and gain fluctuations. Using these expressions we also derive a cost-performance equation that evaluates the gate error probability from its parameter variability, noise, power, and area or redundance. The proposed model is generic for any computing gate in the current digital paradigm. To illustrate the model applicability we calculate the error probability curve for a 90 nm CMOS inverter showing that for this technology the noise is the main limiting factor. A tradeoff analysis of area-power-redundancy-reliability for nanogates is performed indicating that the use of nanoscale individual elements for fabricating gates in deep-nanoscale technologies may not be a viable option. The results clearly suggest that the use of redundant structures is necessary and that averaging structures with mid-high redundancy factors may constitute a reasonable solution for building reliable nanoscale gates.     

Pel reconstruction on FPGA-augmented TriMedia

This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consists of a multiple-context field programmable gate array (FPGA)-based reconfigurable functional unit (RFU), a configuration unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the ED, IQ, and 2-D IDCT tasks, and propose to provide reconfigurable hardware support for a variable-length decoder that can decode two symbols per call (VLD-2), an inverse quantizer that can dequantize four coefficients per call (IQ-4), and an 1-D IDCT (1-D IDCT). The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units are outlined. Experimental results indicate that by configuring each of the VLD-2, IQ-4, and 1-D IDCT units on a different FPGA context, and by activating the contexts as needed, the FPGA-augmented TriMedia can perform MPEG2-compliant pel reconstruction with an average speed-up of 1.4/spl times/ over the standard TriMedia.     

Microcode processing: Positioning and directions

Microcode is an important innovation in computer engineering. the authors discuss the evolution of microcode from its introduction to its decline and to its likely resurgence in custom computing machines. Furthermore, they present a microcoded machine augmented with field-programmable gate arrays (FPGAs) and provide experimental evidence that it can substantially increase the performance of some media benchmarks.     

Computing Division Using Single-Electron Tunneling Technology

Emerging nanotechnologies, like single-electron tunneling (SET) technology, possesses properties that are fundamentally different from what CMOS offers to engineers. This opens up avenues for novel computational paradigms, which can perform arithmetic operations efficiently by utilizing these new available properties. In this line of reasoning, in this paper we investigate the implementation of division in SET technology using a novel computation paradigm called electron counting. First, we present two schemes that are based on sequential approximation of the quotient. The first scheme is basic and simple to build, but suffers from overshoot and has a rather large delay. The second scheme, which is a modification of the first one, has a delay logarithmic in the quotient magnitude and the simulation results we present indicate that this scheme works correctly. Finally, we propose a division scheme based on the computation of periodic symmetric functions. Although this scheme requires a varactor for which no nanoscale implementation yet exists and which cannot be directly simulated, it demonstrates the possibilities that nanotechnology, and specifically SET technology, potentially offers as it has a time complexity of O(1).     

Single electron encoded latches and flip-flops

Single electron tunneling (SET) technology offers the ability to control the transport of individual electrons. In this paper, we investigate single electron encoded logic (SEEL) memory circuits, in which the Boolean logic values are encoded as zero or one electron charges. More specifically, we focus on the implementation of SEEL latches and flip-flops. All proposed circuits are verified by means of simulation using the SIMulation Of Nanostructures package. We first present a generic SEEL linear threshold gate implementation, from which we derive a family of Boolean logic gates. Second, we propose Boolean gate-based implementations of the RS latch, the D latch, and D flip-flop. Third, we propose threshold gate-based implementations of the same memory elements. Finally, we discuss the estimated area, delay, and power consumption of the Boolean gate-based and threshold gate-based implementations, and compare them with other SET-based memory elements.     

Periodic symmetric functions, serial addition, and multiplicationwith neural networks

This paper investigates threshold based neural networks for periodic symmetric Boolean functions and some related operations. It is shown that any n-input variable periodic symmetric Boolean function can be implemented with a feedforward linear threshold-based neural network with size of O(log n) and depth also of O(log n), both measured in terms of neurons. The maximum weight and fan-in values are in the order of O(n). Under the same assumptions on weight and fan-in values, an asymptotic bound of O(log n) for both size and depth of the network is also derived for symmetric Boolean functions that can be decomposed into a constant number of periodic symmetric Boolean subfunctions. Based on this results neural networks for serial binary addition and multiplication of n-bit operands are also proposed. It is shown that the serial addition can be computed with polynomially bounded weights and a maximum fan-in in the order of O(log n) in O(n/log n) serial cycles. Finally, it is shown that the serial multiplication can be computed in O(n) serial cycles with O(log n) size neural gate network, and with O(n log n) latches.     

Cratering response method to study the effect of ultrasonic energy on Cu-wire bonding quality

The paper presents a method for 50 μm Cu-wire bonding to study sub-percentage assembly yield loss due to cratering, so called “in-process” cratering. Test vehicle is an audio amplifier device assembled in a surface mount power package (HSOP). The method is based on high temperature aging followed by wire pull testing and has successfully been applied to determine the upper limit of the bond energy process window. After implementation in production, the shift to lower bond energy was controlled via regular ball shear production monitor and “in-process” cratering was no longer observed.     

Single-electron tunneling transistor implementation of periodic symmetric functions

This paper investigates the implementation of generic periodic symmetric functions (PSFs) with single-electron tunneling transistors (SETTs). The PSF implementation scheme we propose fully utilizes the SETT Coulomb oscillation effect and can properly operate at T>0K, and only a pair of complementary SETTs is required for the implementation of any PSF. Based on the novel PSF block, we propose an analog-to-digital converter (ADC) scheme that requires n PSFs for an n-bit ADC implementation. To demonstrate our approach, a 4-b ADC and a 7|3 counter were designed and verified at 10 K by means of simulation.     

Compositional,Dynamic Cache Management for Embedded Chip Multiprocessors

This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. Because the repartitioning between scenarios requires a cache flush, two undesired effects may occur: (1) in particular, the execution of critical tasks may be disturbed and (2) in general, a performance penalty is involved. To cope with these effects we propose a method which: (1) determines, at design time, the cache footprint of each tasks, such that it creates the premises for critical tasks safety, and minimum flush in general, and (2) enforces, at run-time, the design time determined cache footprints and further decreases the flush penalty. We implement our dynamic cache management strategy on a CAKE multiprocessor with 4 Trimedia cores. The experimental workload consists of 6 multimedia applications, each of which formed by multiple tasks belonging to an extended MediaBench suite. We found on average that: (1) the relative variations of critical tasks execution time are less than 0.1%, regardless of the scenario switching frequency, (2) for realistic scenario switching frequencies the inter-task cache interference is at most 4% for the repartitioned cache, whereas for the shared cache it reaches 68%, and (3) the off-chip memory traffic reduces with 60%, and the performance (in cycles per instruction) enhances with 10%, when compared with the shared cache.