Timely Effective Handover Mechanism in Heterogeneous Wireless Networks

Next-generation wireless networks should be able to coordinate and integrate different communication systems. It has been a challenging problem to support a seamless handover in these diverse wireless network environments. Link level triggers can provide information about events which can help handover decision and layer 3 entities better streamline their handover related activities. In most conventional layer 2 triggering approaches, a pre-defined threshold for a specific perspective such as the received signal strength is used. This may cause too late or too early handover executions. In this paper we propose a new predictive handover framework that uses the neighbor network information to generate timely the link triggers so that the required handover procedures can appropriately finish before the current link goes down. First we estimate a required handover time for the given neighbor network conditions, then using a predictive link triggering mechanism the handover start time is dynamically determined to minimize handover costs. The handover costs are analyzed in terms of the total required handover time and the service disruption time. The numerical analysis and simulation results show that the proposed method significantly enhances the handover performance in heterogeneous wireless networks.     

CCL: a portable and tunable collective communication library forscalable parallel computers

A collective communication library for parallel computers includes frequently used operations such as broadcast, reduce, scatter, gather, concatenate, synchronize, and shift. Such a library provides users with a convenient programming interface, efficient communication operations, and the advantage of portability. A library of this nature, the Collective Communication Library (CCL), intended for the line of scalable parallel computer products by IBM, has been designed. CCL is part of the parallel application programming interface of the recently announced IBM 9076 Scalable POWERparallel System 1 (SP1). In this paper, we examine several issues related to the functionality, correctness, and performance of a portable collective communication library while focusing on three novel aspects in the design and implementation of CCL: 1) the introduction of process groups, 2) the definition of semantics that ensures correctness, and 3) the design of new and tunable algorithms based on a realistic point-to-point communication model     

Area-efficient architectures for the Viterbi algorithm. I. Theory

In the state-parallel implementation of the Viterbi algorithm, one add-compare-select (ACS) unit is devoted to each state in the treillis. A systematic approach to partitioning, scheduling, and mapping N trellis states to P ACSs, where N>P , is presented here. The area saving of this architecture comes from the reduced number of ACSs and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the architecture offers a favorable (smaller) area-time product, compared to the state-parallel implementation     

Architectures for bisdn networks: A performance study

We explore the use of the two current architectures for broadband integrated services digital networks (BISDN) as being defined in IEEE P802.6 (local and metropolitan area network)¹ and ANSI-accredited Committee T1's T1S1.5 baseline document.² The standard currently defines procedures for the median access control (MAC) layer and interfaces for some upper layer services. We, therefore, use the two services defined by the adaptation layer, namely messaging and streaming, to compare their relative performance. It is shown that many conditions are necessary for streaming to out-perform messaging. We then simulate the performance behaviour of these signalling protocols required for the isochronous services of IEEE P802.6 to determine end-to-end delay. This allows us to extend such predictions to the use of IEEE P802.6 as a backbone for concatenated LANs.     

Area-efficient architectures for the Viterbi algorithm II.Applications

In part I the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm were established. Area-efficient architectures for practical codes are presented here to illustrate the design procedures and demonstrate the favourable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes are presented. The application of the area-efficient techniques to codes with a very large number of states, codes with time-varying trellises, and a programmable Viterbi decoder is discussed     

On the Flattest Common Supersequence Method for Deadlock-Free Routing in Arbitrary Networks

In this paper we consider the problem of deadlock-free routing in arbitrary parallel and distributed computers. We focus on asynchronous routing algorithms which continuously receive new packets to route and which do not discard packets that encounter congestion. Specifically, we examine what we call the deadlock-free routing (DFR ) problem. The input to the DFR problem consists of an arbitrary network and an arbitrary set of paths in the network. The output consists of a routing algorithm, which is a list of the buffers used along each of the paths. The routing algorithm is required to be free from deadlock and the goal is to minimize the number of buffers required in any one node. We study the DFR problem by converting it into an equivalent problem which we call the flattest common supersequence (FCS ) problem. The input to the FCS problem consists of a set of sequences and the output consists of a single sequence that contains all of the input sequences as (possibly noncontiguous) subsequences. The goal of the FCS problem is to minimize the maximum frequency of any symbol in the output sequence. We present three main results. First, we prove that the decision version of the FCS problem is NP-complete, and has no polynomial-time approximation scheme unless P= NP . An alternative proof is presented which shows that unlike the shortest common supersequence (SCS) problem, the FCS problem is still NP-complete for two input sequences. This implies that approximation algorithms for FCS based on an exact pairwise merge are not possible. Next, we propose and experimentally evaluate a range of heuristics for FCS. Our experimental results show that one of these heuristics performs very well over a wide range of inputs. Lastly, we prove that this heuristic is in fact optimal for certain restricted classes of inputs. Online publication November 27, 2000.     

Generalized trace-back techniques for survivor memory management in the Viterbi algorithm

In this article, we have studied time-efficient schedule and fault-tolerant design of partitioned array processors for neural networks. First, we have applied the locally-sequential-globally-parallel (LSGP) partitioning scheme to decompose large-size neural network algorithms so that they can be mapped into array processors of smaller size. Then we have derived an optimal latency schedule, i.e., for the same decomposition the schedule outperforms any other schedule, in terms of overall execution time. We have further proposed an algorithm-based fault tolerance (ABFT) method to guarantee higher reliability for the array processor implementation.     

A planar quasi-optical SIS receiver

A planar, quasi-optical SIS (superconductor-insulator-superconductor) receiver operating at 230 GHz is described. The receiver consists of a 2×5 array of half-wave dipole antennas with niobium-aluminum oxide-niobium SIS junctions on a quartz dielectric-filled parabola. The 1.4-GHz intermediate frequency is coupled from the mixer via coplanar strip transmission lines and 4:1 balun transformers. The receiver is operated at 4.2 K in a liquid helium immersion cryostat. Accurate measurements of the performance of single untuned array receiver elements are reported. A mixer noise temperature of 89 K DSB (double sideband), receiver noise temperature of 156 K DSB and conversion loss of 8 dB into a matched load have been obtained. This mixer noise temperature is approximately a factor of two larger than that of current state of the art waveguide mixers using untuned single junctions a the same frequency