A method for consistent fault coverage reporting

Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage     

Modeling the spread of internet worms via persistently unpatched hosts

This article considers the effects of Internet worms on persistently unpatched hosts and hosts for which vulnerabilities are refreshed. Previous models have been homogeneous; that is, all hosts transitioned through the same set of states. The model considered in this article is heterogeneous and more realistic in that subpopulations of hosts are assumed to have inherently different characteristics. Equilibrium conditions are obtained for which an Internet worm will self-propagate indefinitely, which lead to thresholds below which worms will become extinct.     

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain minimal and maximal test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.     

Multiple fault detection in fanout-free combinational networks

In this letter we show that an algorithm developed by Berger and Kohavi for generating minimal length fault-detection test sets for single permanent faults in fanout-free combinational logic networks also detects all possible multiple faults in the network.     

Network Reliability Evaluation Using Probability Expressions

The terminal-pair reliability of a graph (network) is evaluated by means of probability expressions. These expressions result from a transformation of Boolean expressions from the Boolean domain into the probabilistic domain. Basic operations on probability expressions are shown, and a data representation is given for automation of the procedure. The performance of this procedure is compared with other published results. Two new measures, PRI and POST, give relationships between a network's terminal-pair reliability and individual element reliabilities, and derive an element ordering for network diagnosis. These measures can be computed easily using probability expressions.