Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM

As technology continues to scale, maintaining important figures of merit of Static Random Access Memories (SRAMs), such as power dissipation and an acceptable Static Noise Margin (SNM), becomes increasingly challenging. In this paper, we address SRAM instability and power (leakage) dissipation in scaled-down technologies by presenting a novel design flow for simultaneous power minimization, performance maximization and process variation tolerance (P3) optimization of nano-CMOS circuits. The 45 and 32 nm technology node standard 6-Transistor (6T) and 8T SRAM cells are used as example circuits for demonstration of the effectiveness of the flow. Thereafter, the SRAM cell is subjected to a dual threshold voltage (dual-V_Th) assignment based on a novel statistical Design of Experiments-Integer Linear Programming (DOE-ILP) approach. Experimental results show 61% leakage power reduction and 13% increase in the read SNM. In addition, process variation analysis of the optimized cell is conducted considering the variability effect in twelve device parameters. To the best of the authors' knowledge, this is the first study which makes use of statistical DOE-ILP for optimization of conflicting targets of stability and power in the presence of process variations in SRAMs.     

Impact of Temporal Variability on Dopingless and Junctionless FET based SRAM Cells

Silicon - In this brief, we have explored the impact of negative and positive bias temperature instability (NBTI and PBTI) for both DL (dopingless) and conventional junctionless (JL) FET based SRAM...     

Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor

In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results show that the PGFET offers significant reduction in short channel effects and variability due to utilization of uniform lightly doped silicon nanowire (SiNW) as compare to highly doped silicon nanowire in junctionless transistors. The performance parameters were evaluated for different device geometries, such as variation in SiNW radius, equivalent oxide thickness, channel length and spacer length. Sensitivity analysis shows that the PGFET exhibits less dependence towards gate length in comparison to other device parameters. It is seen that ON to OFF current ratio variation with silicon nanowire thickness is lower for PGFET as compared to JLFET. The threshold voltage roll-off and sensitivity towards intrinsic delay in PGFET is much lower than its counterpart device.     

A Raised Source/Drain Dopingless Tunnel FET with Stacked Source: Design and Analysis

Silicon - In this paper, we propose a novel n-type raised source/drain dopingless tunnel field-effect transistor along with stacked source configuration. Using calibrated TCAD 2-D device...     

Design and analysis of DDoS mitigating network architecture

International Journal of Information Security - Distributed Denial of Service (DDoS) attacks have emerged as the top security threat with the rise of e-commerce in recent years. Volumetric attacks...