A MEMS guide plate for a high temperature testing of a wafer level packaged die wafer

This paper describes the design and fabrication of a MEMS guide plate, which was used for a vertical probe card to test a wafer level packaged die wafer. The size of the fabricated MEMS guide plate was 10.6 × 10.6 cm. The MEMS guide plate consisted of 8,192 holes to insert pogo pins, and four holes for bolting between the guide plate and the housing. To insert pogo pins easily, an inclined plane was defined at the back of each hole. Pitch and diameter of the hole were 650 and 260 μm, respectively. In order to define inserting holes and inclined planes at an exact position, silicon MEMS technology was used such as anisotropic etching, deep reactive etching and more. Silicon was used as the material of the guide plate to reduce alignment mismatch between the pogo pins and solder bumps during a high temperature testing. A combined probe card with the fabricated MEMS guide plate showed good x–y alignment and planarity errors within ±9 and ±10 μm at room temperature, respectively. In addition, x–y alignment and planarity are ±20 and ±16 μm at 125°C, respectively. The proposed MEMS guide plate can be applied to a vertical probe card for burn-in testing of a wafer level packaged die wafer because the thermal expansion coefficient of the MEMS guide plate and die wafer is same.     

A new low-cost RF built-in self-test measurement for system-on-chip transceivers

This paper presents a new RF built-in self-test (BIST) measurement and a new automatic-performance-compensation network for a system-on-chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip BIST circuit using 0.18-/spl mu/m SiGe technology. The BIST-measurement circuit contains a test amplifier and RF peak detectors. The complete measurement setup contains an LNA with a BIST circuit, an external RF source, RF relays, 50-/spl Omega/ load impedance, and a dc voltmeter. The proposed BIST circuit measures input impedance, gain, noise figure, input return loss, and output signal-to-noise ratio of the LNA. The test technique utilizes the output dc-voltage measurements, and these measured values are translated to the LNA specifications such as the gain through the developed equations. The performance of the LNA was improved by using the new automatic compensation network (ACN) that adjusts the performance of the LNA with the processor in the SoC transceiver.     

Development of a new automatic fault diagnosis system for fine pattern transmission lines

International Journal of Control, Automation and Systems - This paper presents a new automatic fault diagnosis and detection system for fine pattern interconnects. It is verified by performance of...     

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 μm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive. Jee-Youl Ryu received the BS and MS degrees in 1993 and 1997 from Pukyong National University in Electronic Engineering, Pusan, South Korea respectively. He also received the PhD degree in 2004 from Arizona State University in Electrical Engineering, Arizona, USA. He is currently with Samsung SDI Co., Ltd. His current research interests include RF IC design and testing, MMIC design and testing, analog IC design and testing, passives modeling, testing and analysis, and MEMS technology. Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona in 1985, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He was an Associate Professor at Arizona State University until 2005. Currently, he is an Associate Professor at The University of Alabama. His current research interests include RF IC testing, MEMS integration and VLSI circuits. He has been working on SiP testing technologies, package electrical modeling, and measurements of RF IC packages. Dr. Kim is a 1997 recipient of the National Science Foundation's CAREER Award and received the Meritorious Award from IEEE. He serves as the Chair of the IEEE CPMT Society TC-Electrical Test, associate editor of the IEEE Transactions on Advanced Packaging, associate editor of Design and Test of Computers, and program committee member of Electronic Components and Technology Conference. He is a senior member of IEEE.     

Development of a new automatic control system for the harmonics analysis of distribution transformers

This paper presents a new automatic control system that can precisely and automatically analyze complex harmonics occurring from the power distribution transformers. The proposed system consists of pre-amplification block, digital signal processing block, and real-time monitoring block. It can be applied to a development board with a microcontroller connected to a PC to monitor harmonics in real time because it can be individually affixed to a transformer. The existing expensive harmonics measurement systems take a lot of time to analyze complex harmonics. Unlike the conventional systems, since this system is accurate and automatic in measurement, it provides very low measurement errors and very small test overhead. The proposed system showed very low measurement errors of less than 0.8% as well as fast real-time measurements of approximately 23sec. for harmonics analysis as compared to external expensive equipment measurements. We hope that this new system will provide industry with a simple and inexpensive technique to control and analyze complex harmonics occurring from the distribution transformers.     

A Novel RF Test Scheme Based on a DFT Method

This paper presents a new RF testing scheme based on a design-for-testability (DFT) method for measuring functional specifications of RF integrated circuits (IC). The proposed method provides the input impedance, gain, noise figure, voltage standing wave ratio (VSWR) and output signal-to-noise ratio (SNR) of a low noise amplifier (LNA). The RF test scheme is based on theoretical expressions that produce the actual RF device specifications by utilizing the output DC voltages from the DFT chip. This technique can save marginally failing chips in production testing as well as in the system, hence saving a tremendous amount of revenue from unnecessary device replacements.     

Fabrication of a guide block for measuring a device with fine pitch area-arrayed solder bumps

This paper describes the design and fabrication of a guide block and micro probes, which were used for a vertical probe card to test a chip with area-arrayed solder bumps. The size of the fabricated guide block was 10 mm × 6 mm. The guide block consisted of 172 holes to insert micro probes, 2 guide holes for exact alignment, and 4 holes for bolting between the guide block and the housing of a PCB. Pitch and size of the inserting holes were 80 μm, and 90 μm × 30 μm, respectively. A silicon on insulator wafer was used as the substrate of the guide block to reduce micro probes insertion error. The micro probes were made of nickel–cobalt (Ni–Co) alloy using an electroplating method. The length and thickness of the micro probes were 910 and 20 μm, respectively. A vertical probe card assembled with the fabricated guide block and micro probes showed good x–y alignment and planarity errors within ±4 and ±3 μm, respectively. In addition, average leakage current and contact resistance were approximately 0.35 nA and 0.378 ohm, respectively. The proposed guide block and micro probes can be applied to a vertical probe card to test a chip with area-arrayed solder bumps.     

Low-cost test technique using a new RF BIST circuit for 4.5-5.5 GHz low noise amplifiers

This paper presents a low-cost test technique using a new RF Built-In Self-Test (BIST) circuit for 4.5-5.5 GHz low noise amplifiers (LNAs). The test technique measures input impedance, voltage gain, noise figure, input return loss and output signal-to-noise ratio of the LNA. The BIST circuit is designed using 0.18 μm SiGe technology. The BIST circuit contains test amplifier and RF peak detectors. The complete measurement set-up contains LNA with BIST circuit, external RF source, RF relays, 50 Ω load impedance, and a DC voltmeter. The test technique utilizes output DC voltage measurements and these measured values are translated to the LNA specifications such as input impedance and gain through the developed equations. The technique is simple and inexpensive.