The MC68332 microcontroller

The total-system goals, CPU design goals, and modular design approach of the high-performance MC68332 microcontroller are described. The features of the system integration module, queued serial module, and standby RAM are summarized. The CPU and time processor modules are discussed in detail     

A 512-kb flash EEPROM embedded in a 32-b microcontroller

A 512-kb flash EEPROM developed for microcontroller applications is reported. Many process and performance constraints associated with the conventional flash EEPROM have been eliminated through the development of a new flash EEPROM cell and new circuit techniques. Design of the 512-kb flash EEPROM, which is programmable for different array sizes, has been evaluated from 256- and 384-kb arrays embedded in new 32-b microcontrollers. The 512-kb flash EEPROM has incorporated the newly developed source-coupled split-gate (SCSG) flash EEPROM cell, Zener-diode controlled programming voltages, internally generated erase voltage, and a new differential sense amplifier. It has eliminated overerase and program disturb problems without relying on tight process controls and on critical operational sequences and timings, such as intelligent erase, intelligent program, and preprogram before erase. A modular approach was used for chip design to minimize development time and for processing technology to achieve high manufacturability and flexibility     

Soft-defect detection (SDD) technique for a high-reliability CMOSSRAM

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests     

Multiple steady-states for the oxidation of aqueous ethanol with oxygen on a carbon supported platinum catalyst

The selective oxidation of aqueous ethanol by dioxygen over a platinum on carbon catalyst was investigated in a three-phase continuously stirred tank reactor at a total pressure of 600 kPa, a temperature of 323 K, a pH of 8.4, and a catalyst concentration of 2.3 kg m^–3. Multiple steady-states were obtained by systematic changes in the start-up procedure and variation of the feed concentration of ethanol and partial oxygen pressure in the reactor. The ethanol feed concentration was varied from 100 to 2500 mol m^–3 and the partial oxygen pressure from 8 to 120 kPa. On the time scale of the experiments, i.e. 21 ks, two steady-states of the net disappearance rate of ethanol are observed in the ethanol feed concentration range from 500 to 2500 mol m^–3 at a partial oxygen pressure of 58 kPa and in the range of partial pressure of oxygen from 8 to 120 kPa at an ethanol feed concentration of 500 mol m^–3. Three steady-states are observed in the feed ethanol concentration range from 200 to 400 mol m^–3 and a partial oxygen pressure of 58 kPa.