聚氨酯分散剂在液体靛蓝制备中的应用

采用异佛尔酮二异氰酸酯(IPDI)、聚乙二醇200、400、600、800(PEG200、PEG400、PEG600、PEG800)、2,2-二羟甲基丙酸(DMPA)、1-苯基-1,2-乙二醇、中和剂三乙胺(TEA)、甲乙酮肟等为原料,制备了一种阴离子聚氨酯分散剂.通过FTIR、GPC、TG表征了分散剂的结构与性能.利用自制的分散剂采用研磨法制备了液体靛蓝分散液,以液体靛蓝分散液粒径、离心稳定性、储存稳定性为指标,探讨了分散剂链长、用量对分散液性能的影响.结果表明,研磨1 h后,以PEG400为软段合成的聚氨酯分散剂用量为染料质量的60％时制备的液体靛蓝粒径为277.1 nm,1000 r/min离心稳定性达到93.98％,3000 r/min离心稳定性为51.13％,常温放置7 d后粒径变化在20 nm以内,染色后织物的颜色深度(K/S)为10左右,约是粉状靛蓝染色K/S的2倍,染色织物的颜色性能并未改变,SEM显示分散体颗粒大小分布均匀,与分散剂甲基萘磺酸钠的甲醛缩合物(MF)和木质素85A相比,其分散体系稳定性差别不大.     

Decorative near-infrared transmission filters featuring high-efficiency and angular-insensitivity employing 1D photonic crystals

We present a new scheme for visibly-opaque but near-infrared-transmitting filters involving 7 layers based on one-dimensional ternary photonic crystals, with capabilities in reaching nearly 100% transmission efficiency in the near-infrared region. Different decorative reflection colors can be created by adding additional three layers while maintaining the near-infrared transmission performance. In addition, our proposed structural colors show great angular insensitivity up to ±60° for both transverse electric and transverse magnetic polarizations, which are highly desired in various fields. The facile strategy described here involves a simple deposition method for the fabrication, thereby having great potential in diverse applications such as image sensors, anti-counterfeit tag, and optical measurement systems.

     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Effects of genotype and treatment on the antioxidant activity of sweet potato in Taiwan

Six genotypes of sweet potato commercially available in Taiwan, including TNG57, TNG66, TNG68, TYY1, RP and WP, were used as samples in this study of the effects of steaming and kneading with pre-steaming treatments on the antioxidant components and antioxidant properties of methanolic extracts. Steam treatment increased the total phenols contents of all genotypes (2–13 times), flavonoids content of RP (1.3 times) and anthocyanins contents of RP and WP (5–6 times). Steam treatment also increased the reducing power and scavenging DPPH radical effect of sweet potato flours. For the methanolic extracts of steamed and kneaded flours, reducing powers were 0.02–1.70 at 5.0 mg ml⁻¹ and the scavenging effects on DPPH radicals were 19–92% at 2.5 mg ml⁻¹. Both showed the order of RP > WP > TYY1 and TNG66 > TNG57 and TNG68. However, the chelating effect of the six genotypes at 1.0 mg ml⁻¹ ranged from 50% to 73%. Contents of total phenols, flavonoids, and anthocyanins of sweet potato flours were significantly positively correlated with the reducing power and scavenging DPPH radical effects. After steaming and kneading treatments, RP showed the highest increase in the contents of total phenols, flavonoids and anthocyanins among the six genotypes studied.     

"十一五"规划国家级重点通信项目

《信息产业科技发展“十一五”规划》提出设立部分重大项目,力争实现重点突破,形成一批具有自主知识产权的核心技术和创新产品,打造较为完整的产业链,形成世界一流的产业群。这其中,与通信相关的重点项目主要有:宽带无线移动通信、下一代网络、家庭网络、智能终端、数字电视等。本部分将对我国在以上领域的现状、项目的具体内容和目标、实现这些目标的具体计划以及相关厂商在各领域的努力和成绩进行介绍。