4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOStechnology on SOI, SOS, and bulk substrates

Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 μm CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F_min's of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F_unn's of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 μm CMOS process     

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling     

A kernel‐based core growing clustering method

In this paper, a novel clustering method in the kernel space is proposed. It effectively integrates several existing algorithms to become an iterative clustering scheme, which can handle clusters with arbitrary shapes. In our proposed approach, a reasonable initial core for each of the cluster is estimated. This allows us to adopt a cluster growing technique, and the growing cores offer partial hints on the cluster association. Consequently, the methods used for classification, such as support vector machines (SVMs), can be useful in our approach. To obtain initial clusters effectively, the notion of the incomplete Cholesky decomposition is adopted so that the fuzzy c‐means (FCM) can be used to partition the data in a kernel defined‐like space. Then a one‐class and a multiclass soft margin SVMs are adopted to detect the data within the main distributions (the cores) of the clusters and to repartition the data into new clusters iteratively. The structure of the data set is explored by pruning the data in the low‐density region of the clusters. Then data are gradually added back to the main distributions to assure exact cluster boundaries. Unlike the ordinary SVM algorithm, whose performance relies heavily on the kernel parameters given by the user, the parameters are estimated from the data set naturally in our approach. The experimental evaluations on two synthetic data sets and four University of California Irvine real data benchmarks indicate that the proposed algorithms outperform several popular clustering algorithms, such as FCM, support vector clustering (SVC), hierarchical clustering (HC), self‐organizing maps (SOM), and non‐Euclidean norm fuzzy c‐means (NEFCM). © 2009 Wiley Periodicals, Inc.4     

Flexible complexity reduced PID-like fuzzy controllers

In this paper, a flexible complexity reduced design approach for PID-like fuzzy controllers is proposed. With the linear combination of input variables as a new input variable, the complexity of the fuzzy mechanism of PID-like fuzzy controllers is significantly reduced. However, the performance of the complexity reduced fuzzy PID controller may be degraded since the degree of freedom is decreased by the combination of input variables. To alleviate the drawback and improve the performance of the complexity reduced PID-like fuzzy controller, a flexible complexity reduced design approach is introduced in which the functional scaling factors are heuristically generated. Since the functional scaling factors are heuristically created, they can be easily adjusted for the flexible complexity reduced PID-like fuzzy controller without a priori knowledge of the exact mathematical model of the plant. Moreover, heuristic scaling factors are implemented as functionals. Therefore, the complexity of the flexible PID-like fuzzy controller will not be increased. Further, the stability of the fuzzy control system with a flexible complexity reduced PID-like fuzzy controller is discussed. Finally, the simulation results are also included to show the effectiveness of the PID-like fuzzy controller designed with the flexible complexity reduced approach.     

An approach for the robustness comparison between piecewise linear PID -like fuzzy and classical PID controllers

The comparison of the stability robustness between the classical PID controller and two piecewise linear PID-like fuzzy controllers to the variations of the parameters in the second order plant is provided in this paper. The definition of a stability robust controller (to the parameter variations of the plant model) is presented. Then Kharitonov’s theorem is applied to find the regions of robustness to the parameter variations for the control systems with different controllers. Based on the size of regions of robustness, the relative robustness factor is defined, and the robustness comparison is provided. For every classical PID controller with gain coefficients determined and fixed, it is shown that we can always design the piecewise linear PID-like fuzzy controllers to be more robust than the specific classical PID controller. The results of robustness comparison is further confirmed in the simulation included for the second order uncertain plant.     

Parallel Distributed Fuzzy Sliding Mode Control for Nonlinear Mismatched Uncertain Systems

A new design approach of a parallel distributed fuzzy sliding mode controller for nonlinear systems with mismatched time varying uncertainties is presented in this paper. The nonlinear system is approximated by the Takagi–Sugeno fuzzy linear model. The approximation error between the nonlinear system and the fuzzy linear model is considered as one part of the uncertainty in the uncertain nonlinear system. The time varying uncertainties are assumed to have the format which enables the design of the coefficient matrix of the sliding function to satisfy a sliding coefficient matching condition. With the sliding coefficient matching condition satisfied, a parallel distributed fuzzy sliding mode controller (PDFSC) is designed. The stability and the sliding mode of the fuzzy sliding control system are guaranteed. Also, the nonlinear system is shown to be invariant on the sliding surface. Moreover, the chattering around the sliding surface in the sliding mode control can be reduced by the proposed design approach. Simulation results are included to illustrate the effectiveness of the proposed fuzzy sliding mode controller. This work is partly supported by the the R.O.C. National Science Council through Grant NSC93-2213-E-197-004.     

A two-stage design of adaptive fuzzy controllers for time-delay systems with unknown models

In this article, a systematic two-stage design method for adaptive fuzzy controllers is presented. The proposed control scheme has low computational complexity. Moreover, the exact mathematical model of the plant to be controlled is not required. The fuzzy controller under consideration is based on the proportional-derivative fuzzy control scheme and triangular membership functions. In the design procedure, the domain intervals of the input and output variables are selected with a heuristic approach to minimize a cost function under the constraint of tolerable overshoots in the response curve. A learning scheme is then proposed to automatically adjust the parameters in the fuzzy controller to reduce the error of the system. It can also be used adaptively to improve the system performance of a time-varying system. Simulations and comparisons are included to demonstrate the effectiveness of the proposed method.     

Sidewall oxidation of polycrystalline-silicon gate

Evidence is presented demonstrating that sidewall oxidation, a processing step needed for device reliability, can lead to gate oxide thickening in short-channel devices. This increase in thickness is the result of encroachment of bird's beaks from the edges of the gate structure into the channel region. The encroachment can be reduced by increasing oxidation temperature and/or using a dry ambient. With a judicious choice of polysilicon sidewall oxidation conditions, minimum gate-to-drain overlap capacitance and adequate device reliability can be achieved     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHzfT

We report room-temperature 0.07-μm CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V_dd=1.5 V and I_off ~2.5 nA/μm, minimum L_eff is about 0.085 μm for NFETs and 0.068 μm for PFETs. PFET I_on is 360 μA/μm, which is the highest value ever reported at comparable V_dd and I_off. The SOI MOSFET has about one order of magnitude higher I_off than a bulk MOSFET due to the floating-body effect. At around 0.07 μm L_eff, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications