Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems

Although CAD tools have significantly assisted electronic system simulation, the system-level optoelectronics modeling field has lagged behind due to a lack of simulation methodologies and tools. Optisim, a system-level modeling and simulation methodology of optical interconnects for HPC systems, can provide computer architects, designers, and researchers with a highly optimized, efficient, and accurate discrete-event environment to test various HPC systems.     

Design of a high-speed optical interconnect for scalable shared-memory multiprocessors

Large-scale distributed shared-memory multiprocessors (DSMs) provide a shared address space by physically distributing the memory among different processors. A fundamental DSM communication problem that significantly affects scalability is an increase in remote memory latency as the number of system nodes increases. Remote memory latency, caused by accessing a memory location in a processor other than the one originating the request, includes both communication latency and remote memory access latency over I/O and memory buses. The proposed architecture reduces remote memory access latency by increasing connectivity and maximizing channel availability for remote communication. It also provides efficient and fast unicast, multicast, and broadcast capabilities, using a combination of aggressively designed multiplexing techniques. Simulations show that this architecture provides excellent interconnect support for a highly scalable, high-bandwidth, low-latency network.     

RAPID for high-performance computing systems: architecture and performance evaluation

The limited bandwidth and the increase in power dissipation at longer communication distances and higher bit rates will create a major communication bottleneck in high-performance computing systems (HPCS), affecting not only their performance, but also their scalability. As a solution, we propose an optical-interconnect-based architecture for HPCS called reconfigurable all-photonic interconnect for parallel and distributed systems (RAPID) that alleviates the bandwidth density, optimizes power consumption, and enhances scalability. We also present two cost-effective design alternatives of the architecture, a modified version called M-RAPID and an extended version called E-RAPID that minimizes the cost of the interconnect based on the number of transmitters required. We perform a detailed simulation of the proposed RAPID architecture and compare it to several electrical HPCS interconnects. Based on the performance study, RAPID architecture shows 30%-50% increased throughput and 50%-75% reduced network latency as compared to HPCS electrical networks.     

Al-decorated carbon nanotube as the molecular hydrogen storage medium

Al-decorated, single-walled carbon nanotube has been investigated for hydrogen storage applications by using Density Functional Theory (DFT) based calculations. Single Al atom-decorated on (8,0) CNT adsorbs upto six H₂ molecules with a binding energy of 0.201 eV/H₂. Uniform decoration of Al atom is considered for hydrogen adsorption. The first Al atom has a binding energy of 1.98 eV on (8,0) CNT and it decreases to 1.33 eV/Al and 0.922 eV/Al respectively, when the number of Al atoms is increased to four and eight. Each Al atom in (8,0) CNT-8Al adsorbs four H₂ molecules, without clustering of Al atoms, and the storage capacity reaches to 6.15 wt%. This gravimetric storage capacity is higher than the revised 2015 target of U.S Department of Energy (DOE). The average adsorption binding energy of H₂ in (8,0) CNT-8(Al+4H₂), i.e. 0.214 eV/H₂, lies between 0.20 and 0.60 eV/H₂ which is required for adsorbing and desorbing H₂ molecules at near ambient conditions. Thus, Al-decorated (8,0) CNT is proposed as a good hydrogen storage medium which could be useful for onboard automobile applications, at near ambient conditions.     

H2 adsorption in Ni and passivated Ni doped 4 Å single walled carbon nanotube

Adsorption binding energies have been calculated for Nickel-doped single-walled carbon nanotubes (CNTs). Density Functional Theory (DFT) with double numerical polarization (DNP) has been used for finding the total energies of the structures. It is found that the Nickel doped CNTs show fluctuation in the binding energies of hydrogen adsorption which is overcome by passivating the Nickel atom with two hydrogen atoms. The density of states (DOS) and Mullikan atomic charge analysis have been carried to confirm the charge transfer from Ni to the carbon atoms of the CNT. The smallest CNT (diameter ≈ 4 Å) with the chirality of (5,0) has been taken for hydrogen adsorption studies. Geometry optimization shows that Ni atom prefers bridge site rather than the centre of the hexagon. The H₂ binding energies obtained in the present study reveal that desorption would take place above room temperature in Ni doped (5,0) CNTs.     

Microwave sintering of β-SiAlON–ZrO2 composites

Densification, phase transformation, microstructure evolution and hardness of microwave sintered β-SiAlON–ZrO₂ composites were investigated and compared with conventionally sintered samples. Sintering trials were performed by a high vacuum capable 2.45 GHz microwave furnace without decomposition. Microwave sintered samples showed better densification behavior than conventional sintered samples. The higher density observed in the case of microwave sintered samples was attributed to volumetric fast heating. X-ray diffraction results of conventionally sintered samples showed β-SiAlON, tetragonal ZrO₂ and ZrN phases, while, ZrO₂ reacted with nitrogen and completely transformed to ZrN in the case of microwave sintered samples. The aspect ratios of microwave sintered β-SiAlON grains were higher than conventional sintered samples whereas, hardness remained lower.     

Low-power low-area network-on-chip architecture using adaptive electronic link buffers

In the deep sub-micron regime, the performance of network-on-chip (NoC) architectures is bound by the limited power and area budget. Proposed is a low-power low-area NoC architecture using a novel power-efficient control circuit that enables repeaters along the inter-router links to function as adaptive link buffers, thereby reducing the number of buffers required in the router. Simulation results in the 90 nm technology show power savings of nearly 45% and area savings of 50% for the proposed technique.     

Hydrogen storage in MgH2 coated single walled carbon nanotubes

We present a density functional theory (DFT) study on the hydrogen storage capacity of (5,5) arm-chair single walled carbon nanotubes (SWCNTs) functionalized with magnesium hydride (MgH₂). Being lightweight and rich in hydrogen, MgH₂ adsorbs H₂ molecules in the vicinity of carbon nanotubes. The H₂ molecules are adsorbed dissociatively on SWCNT + MgH₂ complex. The H-H distance gets increased by more than ten times of the initial bond length 0.74 Å of the H₂ molecule. The hydrogen storage capacity of three configurations namely C1MgH₂, C5MgH₂ and C10MgH₂ is reported. The density of states is computed for all the systems. The average binding energies of C5MgH₂ and C10MgH₂ when H₂ molecule is adsorbed are 1.86 eV/H₂ and 1.96 eV/H₂, which are approximately equal. Thus, increasing the number of MgH₂ molecule does not vary the binding energy of H₂ adsorption. The corresponding temperature, in which desorption will take place, is 2285 K and 2457 K for C5MgH₂ and C10MgH₂ systems respectively, which are much above the room temperature.     

RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors

In this paper, we describe the design and analysis of a scalable architecture suitable for large-scale distributed shared memory (DSM) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, numerous shared memory transactions such as requests, responses and acknowledgment messages propagate simultaneously in the network. As the network size increases, network contention results in increasing the critical remote memory access latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called reconfigurable and scalable all-photonic interconnect for distributed-shared memory (RAPID), we provide high connectivity by maximizing the channel availability for remote communication to reduce the critical remote latency. RAPID provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength division multiplexing (WDM), time division multiplexing (TDM), and space division multiplexing (SDM) techniques. RAPID is wavelength-routed, permitting the same limited set of wavelength to be reused among all processors. We evaluated RAPID based on network characteristics, power budget criteria, and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh, and hypercube networks. We found that RAPID outperforms all networks and still provides good performance as the network is scaled to very large numbers.     

Multidimensional and Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems

The increasing demand for higher communication bandwidth, reduced power consumption, and increased reliability combined with fundamental electrical signalling limitations is leading the drive for optics as an interconnect technology of choice for high-performance computing (HPC) systems. However, failure in any optical link can completely disrupt communication by isolating processing nodes in HPC systems. Moreover, while static allocation of wavelengths (channels) provides every node with equal opportunity for communication, it can also lead to network congestion for nonuniform traffic patterns. In this paper, we propose a multidimensional optoelectronic architecture, called nD-reconfigurable, all-photonic interconnect for distributed and parallel systems (ndimensional-RAPID) where n can be 1, 2, or 3. nD-RAPID exploits optical architecture and technology design space that simultaneously tackles both fault-tolerance and dynamic bandwidth reallocation (DBR) of system architecture. Fault-tolerance in nD-RAPID is enabled through a multidimensional architecture. DBR is implemented by the row-column switching matrix using silicon-on-insulator (SOI)-based microring resonators that adapts to changes in communication patterns at runtime. Simulation results indicate that nD-RAPID outperformed other electrical networks for most traffic patterns. Results on DBR show that the proposed row-column switch organization significantly improves throughput and latency with a slight increase in electrical power consumption (~ 0.4% for the worst case traffic).