Source-synchronization and timing vernier techniques for 1.2-GB/sSLDRAM interface

This paper describes a validation system for an SLDRAM interface. The SLDRAM system utilizes two techniques to achieve a high data-transfer rate with a conventional module mounting style. The first technique is a source-synchronization scheme. Since the chip that transmits data also supplies the data clock, the clock and data are completely synchronous. The second is the timing vernier technique. A wait time for output data is programmable in each SLDRAM. Therefore, the time at which data arrive at the controller from any SLDRAM can be set by the controller with a 200-ps step size. The validation chip is designed to emulate these operations. The chip is fabricated using a 0.35-μm CMOS process technology and packaged in a conventional 0.65-mm pitch thin small out-line package, mounted on a single-chip module, and put into an eight-module system. A stub series terminated logic (SSTL)-like interface is adopted for high-speed signals. From system-level measurements, the data eye width of 600 ps is obtained at a data rate of 600 Mbps. Errorless data transmission is observed in both read and write operations in a bit-error rate testing. The validation system has successfully demonstrated a data-transmission rate of 1.2 GB/s (600 Mbit/s/pin) using source-synchronization and timing vernier techniques at the supply voltage of 2.5 V     

Analysis of coupling noise between adjacent bit lines in megabitDRAMs

Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the work-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions the more serious both the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because its thickness and layer position     

A 90-MHz 16-Mb system integrated memory with direct interface toCPU

This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. Also fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-μm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3 mm² is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-bit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants (PDA's), personal computer systems, and embedded controller applications     

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme

A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm² is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity     

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4×32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode     

Advances in DRAM interfaces

New advanced architectures in DRAM interfaces seek to close the ever-widening performance gap between DRAM and microprocessor and to break the bandwidth bottleneck in graphics systems. We present an overview of five of these interfaces: EDO, SDRAM, RDRAM, CDRAM, and 3D-RAM. EDO will soon replace conventional DRAM, and SDRAM will partly take over in 66-MHz and higher frequency systems. Other interfaces will initially find target markets that exploit their unique features, and then seek wider market acceptance. Eventually, advances in DRAM will contribute to the trend toward a system on a chip