Retargetable Code Generation Based on Structural Processor Description

Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approach to achieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to different target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.     

Component-based waveform development: the Nucleus tool flow for efficient and portable software defined radio

With the advent of multi-processor systems on chip (MPSoCs) and due to the complexity and variety of modern wireless standards, academia and industry are moving towards software defined radio (SDR) solutions. It is the goal of the SDR approach to allow designers to describe a radio standard or waveform by means of a high level language. This allows faster waveform development cycles and makes it easier to migrate waveforms across different platforms. Out of many software paradigms, component-based software engineering (CBSE) is an attractive match for SDR, especially for baseband applications. It abstracts waveforms in the traditional way algorithm designers think of their applications and guarantees a high degree of portability. However, existing CBSE approaches for SDR have not been able to close the gap between specification and implementation so as to achieve the computational performance and the energy efficiency of handcrafted solutions. The main reason for this gap is that these flows rely on traditional compilers to lower the high level specification to the platform. The work presented in this paper builds on the Nucleus Concept (Ramakrishnan et al., IEEE Military Communications Conference (MILCOM 2009) [28]) in which computationally intensive kernels and their implementation characteristics on the target platform are known. This information allows a tool to close the performance gap, and thus enables efficient component-based SDR development. In this paper we present such a flow and its supporting environment, which includes state-of-the-art tools for system level design. The flow is demonstrated on a MIMO OFDM transceiver.     

Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths

Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of high-level language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixed-point DSPs. The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraint-based. An initial set of constraints on code generation are prescribed by the given processor model. Further constraints arise during code generation based on decisions concerning code selection, register allocation, and scheduling. Whenever possible, decisions are postponed until sufficient information about a good decision has been collected. The constraints are active in the "background" and guarantee local satisfiability at any point of time during code generation. This mechanism permits to simultaneously cope with special-purpose registers and instruction level parallelism. We describe the detailed integration of code generation phases. The implementation is based on the constraint logic programming (CLP) language ECLiPSe. For a standard DSP, we show that the quality of generated code comes close to hand-written assembly code. Since the input processor model can be edited by the user, also retargetability of the code generation technique is achieved within a certain processor class. This revised version was published online in July 2006 with corrections to the Cover Date.     

Compiler design issues for embedded processors

The growing complexity and high efficiency requirements of embedded systems call for new code optimization techniques and architecture exploration, using retargetable C and C++ compilers. The first commercial tools are already in industrial use. Meanwhile, researchers are developing new processor-specific code generation techniques that continually narrow the code quality gap between C compilers and assembly programming. The approaches that achieve the right balance of flexibility, code quality, retargeting effort, and compatibility with existing design tools will be successful     

Functional analysis of Ran/TC4 as a protein regulating T-cell costimulation

Antigen (Ag)-triggered activation of T cells requires engagement of both the T-cell Ag receptor and a costimulatory receptor, for which CD28 can function as a prototypical example. CD80 and CD86 represent ligands for this receptor, and although they are present on professional Ag-presenting cells, these molecules are absent from most tumors. Yet some tumors are still able to costimulate a T-cell response, while others cannot. Therefore, a key question concerns the molecular basis for the costimulation of T cells by those tumor cells not expressing the CD28 ligands CD80 and CD86. Upon screening a cDNA library of such a tumor cell line in a transient COS cell transfection assay for costimulatory activity, we identified Ran/TC4 as a protein whose overexpression results in costimulatory activity. Ran/TC4 is a ubiquitously expressed member of the Ras gene superfamily of small guanosine triphosphate-binding proteins and is involved in nuclear transport; Ran/TC4 cDNA-transfected COS cells specifically costimulate CD8 T cells and not CD4 T cells. Transfection of Ran/TC4 into the costimulation-deficient murine RMA lymphoma cell line introduced costimulatory capacity for CD8 T cells and resulted in markedly elevated levels of nuclear Ran/TC4 protein expression. In addition, in vivo priming of mice with Ran/TC4-transfected RMA cells induced protection against wild-type (wt) RMA tumor cells. Ran/TC4-transfected RMA cells and wt RMA tumor cells exhibit comparable in vivo growth rates in mice lacking T and B cells, and Ran/TC4-mediated tumor rejection thus involves B and/or T cells. This possibility is substantiated by the observation that T cells from normal mice challenged with Ran/TC4-transfected RMA cells can mount a cytotoxic T-cell response not only against the Ran/TC4-transfected tumor cells but also against wt RMA tumor cells. Based on these results, we conclude that gene transfer-mediated elevations in Ran/TC4 can confer costimulatory function for CD8 T cells to tumor cells. This finding suggests a novel application of Ran/TC4 as a protein capable of regulating costimulation in tumor cells.