A knowledge-based expert system for automatic visual VLSI reverse-engineering: VLSI layout version

This paper presents a method of knowledge representation for very large scale integration (VLSI) chip design which provides the necessary information for abstraction from the physical design to gate-level logic through a high-level behavioral model. The representation scheme used by the ANTISTROFEAS system utilizes a hierarchical attributed graph structure which consists of incrementally abstracted design information for the VLSI system. This method of knowledge representation is well-suited to reverse-engineering of VLSI chips from the layer mask layout data, but is also applicable to applications at many levels of the design process including design rule checking, logic synthesis, design verification, and partitioning-compaction problems. The representation scheme is applicable to any VLSI technology, and is designed to take advantage of artificial intelligence. expert system techniques, by disassociating the representation and manipulation of the VLSI design data from the rules which govern its correctness and transformation for other usage.     

A digital retina-like low-level vision processor

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.