Efficient designs of reversible sequential circuits

The Journal of Supercomputing - Recently, the synthesis of reversible sequential circuits has attracted researchers’ attention for implementing low-power logic designs. So far, the direct and...     

The cost-effective fault detection and fault location approach for communication channels in NoC

In the current paper, we propose a new online search, fault detection, and fault location approach for short faults in network on chip communication channels. The approach proposed consists of a built-in self-test as well as a packet/flit comparings module embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, firstly, the diagnosis and location processes are simultaneously carried out after which the test time is minimized. Secondly, the approach updates the NoC routing tables far less costly in a parallel fashion. Thirdly, insignificant hardware is added to the system. The high scalability in the approach, in addition, leads to 100% test coverage, 71.4% capability of detecting faulty channels, and 100% detected faults location in one round (two phases). The simulation results show that the approach hardware is optimized compared with the previous methodologies.     

A routing algorithm for reducing optical loss in photonic Networks-on-Chip

Driven by increase in automation, smart homes play an important role in today’s human life. This paper presents a new model for smart home technologies based on multi-device bidirectional visible light communication (VLC). For multiple devices and users, orthogonal code-based wavelength division (color beams) full-duplexed bidirectional VLC link is proposed. The color beams from RGB LEDs are utilized to transmit data and synchronize multi-device transmission. To enhance the performance of the proposed model, receiver diversity is also employed. Performance evaluation reveals that the proposed VLC-based model for smart homes is efficient with superior BER performance in a typical smart home environment except for the far corners. The maximum achievable data rate for each user up to four users is found to be 24 Mbps at both uplink and downlink transmissions.     

Efficient binary to quaternary and vice versa converters: embedding in quaternary arithmetic circuits

The Journal of Supercomputing - Reversible logic is a nowadays promising choice for circuit design technologies since it is having diversified applications in the fields of digital signal...     

Low-cost regional-based congestion-aware routing algorithm for 2D mesh NoC

Given the advantages of network-on-chips (NoCs), they are rapidly improving to replace other forms of System-on-Chip (SoC) designs. Although various factors improve the NoC's performance, many challenges should be addressed when designing an NoC, one of which is congestion and its impacts on performance and efficiency. Hence, numerous routing algorithms have been proposed that contemplate the congestion influences to deal with its complexities. Nevertheless, given the significant impacts of overheads on performance and efficiency, it is crucial to consider them when designing an enhanced NoC. The proposed routing algorithm employs regional traffic information within multiple clusters and has a decent view of the traffic condition when choosing the path to the destination. Each node generates one bit of traffic information and propagates it only when the node is congested, thus preventing the information overhead. Finally, the path diversity parameter is utilized to identify the best route from the source to the destination. The proposed algorithm's results show that the number of received packets, average latency, average throughput, maximum latency, and energy consumption while using different traffic patterns are improved by 10.9%, 35.3%, 15.8%, 43%, and 15.3%, respectively.     

Correction to: Asymmetric RF MEMS resonant switch for high speed switching applications

Microsystem Technologies - Unfortunately, the affiliation details of the authors have been published incorrectly. The correct details are given below.     

Asymmetric RF MEMS resonant switch for high speed switching applications

Microsystem Technologies - Although micro-electro-mechanical switches are beneficial in small sizes, high levels of power handling, compatibility with CMOS process, wide bandwidth and zero power...     

Designing a MapReduce performance model in distributed heterogeneous platforms based on benchmarking approach

MapReduce framework is an effective method for big data parallel processing. Enhancing the performance of MapReduce clusters, along with reducing their job execution time, is a fundamental challenge to this approach. In fact, one is faced with two challenges here: how to maximize the execution overlap between jobs and how to create an optimum job scheduling. Accordingly, one of the most critical challenges to achieving these goals is developing a precise model to estimate the job execution time due to the large number and high volume of the submitted jobs, limited consumable resources, and the need for proper Hadoop configuration. This paper presents a model based on MapReduce phases for predicting the execution time of jobs in a heterogeneous cluster. Moreover, a novel heuristic method is designed, which significantly reduces the makespan of the jobs. In this method, first by providing the job profiling tool, we obtain the execution details of the MapReduce phases through log analysis. Then, using machine learning methods and statistical analysis, we propose a relevant model to predict runtime. Finally, another tool called job submission and monitoring tool is used for calculating makespan. Different experiments were conducted on the benchmarks under identical conditions for all jobs. The results show that the average makespan speedup for the proposed method was higher than an unoptimized case.

     

Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip

The Journal of Supercomputing - Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips...