Improved performance of an engineering model cryogen free double adiabatic demagnetization refrigerator

This paper describes the design, development and performance of the engineering model double adiabatic demagnetization refrigerator (dADR) built and tested under contract to the European Space Agency for its former mission XEUS (now IXO). The dADR operates from a 4 K bath and has a measured recycle and hold time (with a parasitic load of 2.34 μW) at 50 mK of 15 h and 10 h, respectively. It is shown that the performance can be significantly improved by operating from a lower bath temperature and replacing the current heat switches with tungsten magnetoresistive (MR) heat switches, which significantly reduce the parasitic heat load. Performing the latter gives an anticipated recycle and hold time of 2 and 29 h (with a 1 μW applied heat load in addition to the parasitic load), respectively. Such improved performance allows for a reduction in mass of the dADR from 32 kg to 10 kg by operating from a 2.5 K bath (which could be reduced further by optimising the magnet design). Ultimately, continuous operation could be achieved by linking two dADRs to a common detector stage and operating them alternately. Based on this design the mass of the continuous ADR is estimated to be about 4.5 kg.     

A model of invariant object recognition in the visual system: learning rules, activation functions, lateral inhibition, and information-based performance measures

VisNet2 is a model to investigate some aspects of invariant visual object recognition in the primate visual system. It is a four-layer feedforward network with convergence to each part of a layer from a small region of the preceding layer, with competition between the neurons within a layer and with a trace learning rule to help it learn transform invariance. The trace rule is a modified Hebbian rule, which modifies synaptic weights according to both the current firing rates and the firing rates to recently seen stimuli. This enables neurons to learn to respond similarly to the gradually transforming inputs it receives, which over the short term are likely to be about the same object, given the statistics of normal visual inputs. First, we introduce for VisNet2 both single-neuron and multiple-neuron information-theoretic measures of its ability to respond to transformed stimuli. Second, using these measures, we show that quantitatively resetting the trace between stimuli is not necessary for good performance. Third, it is shown that the sigmoid activation functions used in VisNet2, which allow the sparseness of the representation to be controlled, allow good performance when using sparse distributed representations. Fourth, it is shown that VisNet2 operates well with medium-range lateral inhibition with a radius in the same order of size as the region of the preceding layer from which neurons receive inputs. Fifth, in an investigation of different learning rules for learning transform invariance, it is shown that VisNet2 operates better with a trace rule that incorporates in the trace only activity from the preceding presentations of a given stimulus, with no contribution to the trace from the current presentation, and that this is related to temporal difference learning.     

The Reconfigurable Instruction Cell Array

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.     

Cluster computing and grid 2005 works in progress

The first in a two-part series of works-in-progress articles from cluster computing and grid 2005 deals with a project called Grid-Oriented Storage (GOS). GOS aims to support advanced data bank services and data reservoirs so that multiple computers and end users can share data on the grid. The second part deals with a dynamic estimation scheme for fault-free scheduling in grid systems.     

Design and implementation of a lossless parallel high-speed data compression system

Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.