全文获取类型
收费全文 | 61篇 |
免费 | 13篇 |
专业分类
电工技术 | 3篇 |
化学工业 | 6篇 |
金属工艺 | 1篇 |
机械仪表 | 1篇 |
建筑科学 | 2篇 |
能源动力 | 5篇 |
轻工业 | 2篇 |
无线电 | 26篇 |
一般工业技术 | 19篇 |
原子能技术 | 1篇 |
自动化技术 | 8篇 |
出版年
2023年 | 7篇 |
2022年 | 2篇 |
2021年 | 2篇 |
2020年 | 1篇 |
2018年 | 9篇 |
2017年 | 2篇 |
2016年 | 3篇 |
2015年 | 2篇 |
2014年 | 4篇 |
2013年 | 4篇 |
2012年 | 9篇 |
2011年 | 7篇 |
2010年 | 1篇 |
2009年 | 6篇 |
2008年 | 1篇 |
2005年 | 2篇 |
2004年 | 1篇 |
2003年 | 4篇 |
2002年 | 3篇 |
2000年 | 1篇 |
1998年 | 2篇 |
1993年 | 1篇 |
排序方式: 共有74条查询结果,搜索用时 46 毫秒
1.
Jae Kyeong Jeong Jong Han Jeong Hui Won Yang Tae Kyung Ahn Minkyu Kim Kwang Suk Kim Bon Seog Gu Hyun‐Joong Chung Jin‐Seong Park Yeon‐Gon Mo Hye Dong Kim Ho Kyoon Chung 《Journal of the Society for Information Display》2009,17(2):95-100
Abstract— A full‐color 12.1‐in.WXGA active‐matrix organic‐light‐emitting‐diode (AMOLED) display was, for the first time, demonstrated using indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) as an active‐matrix backplane. It was found that the fabricated AMOLED display did not suffer from the well‐known pixel non‐uniformity in luminance, even though the simple structure consisting of two transistors and one capacitor was adopted as the unit pixel circuit, which was attributed to the amorphous nature of IGZO semiconductors. The n‐channel a‐IGZO TFTs exhibited a field‐effect mobility of 17 cm2/V‐sec, threshold voltage of 1.1 V, on/off ratio >109, and subthreshold gate swing of 0.28 V/dec. The AMOLED display with a‐IGZO TFT array is promising for large‐sized applications such as notebook PCs and HDTVs because the a‐IGZO semiconductor can be deposited on large glass substrates (larger than Gen 7) using the conventional sputtering system. 相似文献
2.
In this article, the method for increasing dynamic stability of quadruped robot is proposed. Previous researches on dynamic
walking of quadruped robots have used only walking pattern called central pattern generator (CPG). In this research, different
from walking generation with only CPG, a instinctive stability measure called landing accordance ratio, is proposed and used
for increasing dynamic stability. In addition, dynamic balance control and control to adjust walking trajectory for increasing
dynamic stability measure is also proposed. Proposed methods are verified with dynamic simulation and a large number of experiments
with quadruped robot platform. 相似文献
3.
4.
As the thickness of crystalline silicon solar cells decreases, light loss cannot be avoided due to the absorption limit in long wavelength light. Internal rear side reflection can be enhanced by polishing the rear surface. The rear polishing processes are performed before the texturing and before and after doping the emitter layer to optimize the solar cell fabrication process sequences. All cells made by rear surface polishing showed improved light trapping in long wavelength region (900-1100 nm) compared to that in the conventional cells. However, silicon solar cells fabricated by rear polishing before and after doping have similar (35.5 mA/cm2) or lower (35.26 mA/cm2) short circuit current density compared to the cells produced by the conventional process (35.59 mA/cm2) due to pore damage to the anti-reflection layer and the surface of the emitter layer during rear polishing. This surface damage was effectively prevented adapting the rear surface polishing before the front surface texturing, which led to increasing the current density from 35.59 to 36.29 mA/cm2. 相似文献
5.
6.
Junho Moon Minkyu Song Seungchul Shin Kyungho Moon Byungha Park 《Analog Integrated Circuits and Signal Processing》2010,63(3):407-414
A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter
is based on the current steering 6 + 6 segmented type with a laminated current cell relocation technique. In order to improve
the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing
the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify
its performance, the chip was fabricated with 0.13 μm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective
chip area is 0.26 mm2 (510 × 510 μm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The
measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz. 相似文献
7.
Hyunwoong Seo Minkyu Son Jitae Hong Dong-Yoon Lee Tae-Pung An Hyunju Kim Hee-Je Kim 《Solar Energy》2009,83(12):2217-2222
Large dye-sensitized solar cells (DSCs) are usually fabricated as module types instead of single cell types, because the overall efficiency of an area-expanded single DSC is decreased by its large surface resistances and low fill factor (FF). The general DSC module designs are the parallel grid, series interconnect, and series monolithic types. The W-series interconnect type of module has some advantages, such as its easy fabrication and simple structure. Moreover, it also avoids the reduction in the FF. However, it has an efficiency imbalance between the single cells, because of the discrepancy in their luminous intensity. Therefore, the fabrication of the W-series interconnect type of module will be cost-effective only if the problem of its efficiency imbalance is solved. In this study, the thickness of the Pt layer, which has a very high reflection rate, and that of the electrolyte layer are minimized and the transmitted light is reflected by a metallic thin film in order to increase the number of photons absorbed by the dye molecules in the module. As a result, the performance of the efficiency-balanced W-module is improved by approximately 1% as compared to that of the conventional module. 相似文献
8.
Minkyu Song Yongman Lee Wonchan Kim 《Solid-State Circuits, IEEE Journal of》1993,28(2):133-137
A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20% 相似文献
9.
Jaewoo Choi Nagarajan Balaji Vinh Ai Dao Cheolmin Park Seunghwan Lee Jungmo Kim Minkyu Ju Hoongjoo Lee Youn-Jung Lee Junsin Yi 《Journal of Electronic Materials》2014,43(9):3191-3195
The effect of hydrogen capping of SiN(Si-rich)/SiN(N-rich) stacks for n-type c-Si solar cells was investigated. Use of a passivation layer consisting of Si-rich SiN with a refractive index (n) of 2.7 and N-rich SiN with a refractive index of 2.1 improved the thermal stability. A single SiN passivation layer with a refractive index of 2.05 resulted in an initial lifetime of 200 μs whereas the layer with a refractive index of 2.7 resulted in a high initial lifetime of 2 ms, but the layer degraded rapidly after firing. A stacked passivation layer with refractive indices of 2.1 and 2.7 had a stable lifetime of 1.5 ms with an implied open-circuit voltage (iV oc) of 720 mV after firing. The thermally stable passivation mechanism with changing amounts of Si–N and Si–H bonding was analyzed by Fourier-transform infrared (FTIR) spectroscopy. Incorporation of the SiN x stack layer (2.7 + 2.1) into the passivated rear of n-type Cz silicon screen-printed solar cells resulted in energy conversion efficiency of 19.69%. Improved internal quantum efficiency in the long-wavelength range above 900 nm, with V oc of 630 mV, is mainly because of superior passivation of the rear surface compared with conventional solar cells. 相似文献
10.
A highly efficient single-input, dual-output AC–DC converter for wireless power transfer in implantable devices is implemented using the 0.18-µm CMOS process. The proposed AC–DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm2. 相似文献