C-Testable modified-Booth multipliers

In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an N _x × N_y bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.     

Handling zero in diminished-one modulo 2 n + 1 adders

Zero treatment in diminished-one modulo 2 ⁿ + 1 addition has traditionally been performed separately, leading to slow and area-consuming implementations. To overcome this, on the basis of an enhanced number representation used previously, we introduce novel carry look ahead and parallel-prefix architectures for diminished-one modulo 2 ⁿ + 1 adders that can also handle operands equal to 0. Translators for the new representation are also given.     

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our technique eliminates the need of a ROM for storing the seeds since the reseeding is performed on-the-fly by inverting the logic value of some of the bits of the next state of the Test Pattern Generator (TPG). The proposed reseeding technique is generic and can be applied to TPGs based on both Linear Feedback Shift Registers (LFSRs) and accumulators. An efficient algorithm for selecting reseeding points is also presented, which targets complete fault coverage and allows to well exploiting the trade-off between hardware overhead and test length. Using experimental results we show that the proposed method compares favorably to the other already known techniques with respect to test length and the hardware implementation cost.     

Testable Designs of Multiple Precharged Domino Circuits

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults     

Evolutionary algorithm based offline/online path planner for UAV navigation

An evolutionary algorithm based framework, a combination of modified breeder genetic algorithms incorporating characteristics of classic genetic algorithms, is utilized to design an offline/online path planner for unmanned aerial vehicles (UAVs) autonomous navigation. The path planner calculates a curved path line with desired characteristics in a three-dimensional (3-D) rough terrain environment, represented using B-spline curves, with the coordinates of its control points being the evolutionary algorithm artificial chromosome genes. Given a 3-D rough environment and assuming flight envelope restrictions, two problems are solved: i) UAV navigation using an offline planner in a known environment, and, ii) UAV navigation using an online planner in a completely unknown environment. The offline planner produces a single B-Spline curve that connects the starting and target points with a predefined initial direction. The online planner, based on the offline one, is given on-board radar readings which gradually produces a smooth 3-D trajectory aiming at reaching a predetermined target in an unknown environment; the produced trajectory consists of smaller B-spline curves smoothly connected with each other. Both planners have been tested under different scenarios, and they have been proven effective in guiding an UAV to its final destination, providing near-optimal curved paths quickly and efficiently.     

An efficient built-in self test method for robust path delay fault testing

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.     

Sorter Based Permutation Units for Media-Enhanced Microprocessors

Single or multibit subword permutations are useful in many multimedia and cryptographic applications. Several specialized instructions have been proposed to handle the required data rearrangements. In this paper, we examine the hardware implementation of the powerful permutation instruction group (GRP). The design of the proposed permutation unit is based on the functionality of sorting networks. Two variants of the sorter-based GRP unit are introduced and analyzed and their energy-delay behavior is investigated using static CMOS implementations in a 130-nm CMOS technology.     

Artificial Neural Network (ANN) Based Modeling for Karstic Groundwater Level Simulation

A relatively new method of addressing different hydrological problems is the use of artificial neural networks (ANN). In groundwater management ANNs are usually used to predict the hydraulic head at a well location. ANNs can prove to be very useful because, unlike numerical groundwater models, they are very easy to implement in karstic regions without the need of explicit knowledge of the exact flow conduit geometry and they avoid the creation of extremely complex models in the rare cases when all the necessary information is available. With hydrological parameters like rainfall and temperature, as well as with hydrogeological parameters like pumping rates from nearby wells as input, the ANN applies a black box approach and yields the simulated hydraulic head. During the calibration process the network is trained using a set of available field data and its performance is evaluated with a different set. Available measured data from Edward??s aquifer in Texas, USA are used in this work to train and evaluate the proposed ANN. The Edwards Aquifer is a unique groundwater system and one of the most prolific artesian aquifers in the world. The present work focuses on simulation of hydraulic head change at an observation well in the area. The adopted ANN is a classic fully connected multilayer perceptron, with two hidden layers. All input parameters are directly or indirectly connected to the aquatic equilibrium and the ANN is treated as a sophisticated analogue to empirical models of the past. A correlation analysis of the measured data is used to determine the time lag between the current day and the day used for input of the measured rainfall levels. After the calibration process the testing data were used in order to check the ability of the ANN to interpolate or extrapolate in other regions, not used in the training procedure. The results show that there is a need for exact knowledge of pumping from each well in karstic aquifers as it is difficult to simulate the sudden drops and rises, which in this case can be more than 6 ft (approx. 2 m). That aside, the ANN is still a useful way to simulate karstic aquifers that are difficult to be simulated by numerical groundwater models.     

Self-Testing Embedded Two-Rail Checkers

This paper presents a new simple and straightforward method for designing Completely Testable Embedded (CTE) parity trees, and Self-Testing Embedded (STE) two-rail checkers. In the design of CTE parity trees the two inputs XOR gate has been used as the building block. In the case of STE two-rail checkers with n input pairs the building block is the two-rail checker with 2 input pairs. During normal, fault free, operation each XOR gate receives all possible input vectors, while each two-rail checker with 2 input pairs receives all possible code input vectors. The great advantage of the proposed method is that it is the only one that gives in a simple and straightforward way an optimal CTE/STE tree realization with respect to the hardware (number of blocks) and the speed (number of block levels). Designing the two input two-rail checker as proposed by Lo in IEEE J. of Solid-State Circuits, 1993, we get optimal STE two-rail checkers taking into account realistic faults.     

Path delay fault testing of multiplexer-based shifters

In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are not single path propagating hazard free robustly testable (SPP-HFRT) and we present a path selection method such that all the selected paths are SPP-HFRT by (Olog₂ n) test-vector pairs, where n is the length of the shifter's operand. The propagation delay along all other paths is a function of the delays along the selected paths. This is the first work addressing the problem of shifter path delay fault testing.