Effect of Precursor and Solvent on Morphology of Zirconia Nanoparticles Produced by Combustion Aerosol Synthesis

Zirconia nanoparticles were synthesized using a flame-based system involving spray droplet combustion of different precursor solutions. The characteristics of the feed were varied by varying the precursor compound, precursor concentration, and solvent type, and by using droplets of different mean sizes. When large droplets were used, agglomerated particles were formed when an organometallic precursor was used and large cenospheric particles were produced when an inorganic precursor was used. Reduction of the droplet size to a number-mean droplet diameter of 3.2 μm resulted in the production of solid spherical particles regardless of the precursor type. When an inertial impactor was used to eliminate droplets larger than 2.3 μm, the large particles in the final product were eliminated and uniformly sized solid zirconia particles having a smaller mean size were produced. The final particle size did not vary with the concentration of the precursor, indicating that multiple ceramic particles resulted from each precursor-containing droplet.     

Counting Paths in VPA Is Complete for #NC 1

We give a #NC ¹ upper bound for the problem of counting accepting paths in any fixed visibly pushdown automaton. Our algorithm involves a non-trivial adaptation of the arithmetic formula evaluation algorithm of Buss, Cook, Gupta and Ramachandran (SIAM J. Comput. 21:755?C780, 1992). We also show that the problem is #NC ¹ hard. Our results show that the difference between #BWBP and #NC ¹ is captured exactly by the addition of a visible stack to a nondeterministic finite-state automaton.     

Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware

Designing hardware often involves several types of modeling and analysis, e.g., in order to check system correctness, to derive performance properties such as throughput, to optimize resource usages (e.g., buffer sizes), and to synthesize parts of a circuit (e.g., control logic). Working directly with low-level hardware models such as finite-state machines (FSMs) to answer such questions is often infeasible, e.g., due to state explosion. Instead, designers often use dataflow models such as SDF and CSDF, which are more abstract than FSMs, and less expensive to use since they come with more efficient analysis algorithms. However, dataflow models are only abstractions of the real hardware, and often omit critical information. This raises the question, when can one say that a certain dataflow model faithfully captures a given piece of hardware? The question is of more than simply academic interest. Indeed, as illustrated in this paper, dataflow-based analysis outcomes may sometimes be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). To answer the question of faithfully capturing hardware using dataflow models, we develop a formal conformance relation between the heterogeneous formalisms of (1) finite-state machines with synchronous semantics, typically used to model synchronous hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.     

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache

This paper describes a dual-core 64-b Xeon MP processor implemented in a 65-nm eight-metal process. The 435-mm² die has 1.328-B transistors. Each core has two threads and a unified 1-MB L2 cache. The 16-MB shared, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes. Long channel transistors are used to reduce subthreshold leakage in cores and uncore (all portions of the die that are outside the cores) control logic. Multiple voltage and clock domains are employed to reduce power     

Cytomegalovirus disease occurring before engraftment in marrow transplant recipients

We developed a novel approach for the high-level production of a microbial transglutaminase (TGase) from Streptoverticillium in E. coli. The direct expression of the TGase gene in E. coli cells did not cause overproduction, probably due to the harmful influence of TGase activity, which introduces covalent crosslinks between proteins. Therefore, we fused the chemically synthesized TGase gene coding for the entire 331 amino acid residues at the amino terminus to a bacteriophage T7 gene 10 leader peptide (260 amino acids) using an inducible expression vector. The TGase gene was expressed as inclusion bodies in the E. coli cytoplasm. Restoring 15 amino acid residues upstream of the amino terminus of the mature TGase by a two-step deletion of the fusion sequence facilitated solubilization and subsequent proteolytic cleavage, thus releasing mature TGase. Although the mature form had less TGase activity than native TGase, because of the poor refolding rate, these results suggest that this system is suitable for the efficient production of TGase.     

Characterization of aluminides formed on superalloy 690 substrate

Ni-Cr-Fe based superalloy 690 substrate, pack aluminized at 1273 K, revealed formation of multilayer comprising (NiCr)Al + Cr₅Al₈, Ni₂Al₃ + Cr₅Al₈, NiAl and γ phases. Knoop hardness number varied from 225 to 1142 along the cross-section. Wear and friction tests on aluminized specimen were performed in dry medium using reciprocating sliding wear and friction machine with tungsten carbide ball at 15 N load with frequencies at 10, 15 and 20 Hz. The coefficient of friction, the static ones were obtained in the vicinity of 0.2, 0.3 and 0.5, while dynamic ones were 0.3, 0.4 and 0.4 respectively. For the ball, the wear rate was 1.9 × 10^?6, 1.2 × 10^?5 and 1.5 × 10^?5 mm³/Nm, whereas the wear rate was 5.8 × 10^?5, 3.8 × 10^?4 and 4.6 × 10^?4 mm³/Nm respectively for the aluminized specimen indicating good adherent surface coating.     

Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.