Embedded deterministic test for low-cost manufacturing

You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.     

Testability implications of performance driven logic synthesis

Retiming improves performance but also increases test generation time and decreases fault coverage. Research conducted at Carnegie Mellon and McGill Universities attempts to explain the impact of retiming on the testability of sequential logic circuits. A novel test preservation theorem suggests a powerful way to decrease the test generation cost of retimed circuits. The authors also discuss a recently recognized circuit attribute that better explains the complexity of structural, sequential automatic test pattern generation     

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

Self-reconfiguring interconnection network for a fault-tolerantmesh-connected array of processors

An interconnection network capable of spontaneously reconfiguring a mesh-connected processor array on detection of faulty processors is presented. Although the reconfiguration process is global in nature, the network control circuitry is localised around each processor and is therefore completely modular. In addition, the structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors     

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis

This article describes a two-stage test response compactor with an overdrive section, scan chain selection logic, and an on-chip comparator and registration scheme for efficient signature-based diagnosis. This solution offers compaction ratios much higher than those determined by the ratio of scan chains to compactor outputs, and it guarantees very good observability and diagnostic resolution of scan errors, even for a large number of Xs. Experimental results confirm that the proposed solution does not compromise test quality and requires a minimal amount of information to control the compactor itself.     

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal—spatial and time—signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.     

Reconvergent fanout analysis and fault simulation complexity of combinational circuits

The detectability of reconvergent fanout stem faults in a combinational logic circuit can be determined by explicitly simulating the faults within limited regions of the circuit. These regions are defined, and an estimate of the fault simulation complexity of the circuit is obtained. Results are presented for ten benchmark circuits.     

The Effect of Choosing the Switches for Rearrangements in Switching Networks

Known rearrangement algorithms proposed by Slepian and Paull (method 1) involve two middle switches of the three-stage Clos network. These switches are chosen arbitrarily. However, the middle switches selection rules affect the rearrangement process. In this paper four methods for choosing the switches were studied. Simulation results and analysis have shown that the allocation of the least used switches can decrease the volume of computation required for rearrangements. In the case of limited rearrangement, this method improves the blocking performance of a network.