Effect of dry‐heat treatments on the nutritional value of maize germ

Maize germ is a by‐product of the maize milling process that is characterised by a high nutritional value. Currently, heat treatments are employed to prevent full‐fat maize germ from spoilage. The aim of this research was to study the effect of five dry‐heat treatments on the nutritional value of full‐fat maize germ. The results confirmed that after each dry‐heat treatment, the lipase activity decreases but the use of high temperatures could be detrimental for phytosterol and thiamine concentrations. The main negative effects have been observed after treatments at 140 °C for 30 min and 160 °C for 10 min. No significant difference has been observed for protein, ash or fatty acid contents. The treatment at 140 °C for 20 min resulted an optimal combination between temperature and heating time to inactivate lipase without altering deeply the nutritional value and the colour of maize germ.     

A High Speed VLSI Architecture for Handwriting Recognition

This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).     

Bioactive compound content,antioxidant activity,deoxynivalenol and heavy metal contamination of pearled wheat fractions

Wheat kernels are rich in antioxidant compounds, that are mainly present in the outer bran layers and which are removed during milling. Unfortunately, several contaminants, e.g., mycotoxins and heavy metals, are also concentrated in the external layers. Pearling of 3 wheat varieties gave five fractions (each 5% of the original grain weight), starting from the outer layer until the inner kernel, designated as 0–5%, 5–10%, 10–15%, 15–20%, 20–25%, respectively. The remaining 75% of the inner kernel was also collected. Dietary fibre, free phenolic acids and total antioxidant activity decreased progressively from the external to the internal layers. However, the 5–10% fraction was richer in β-glucan content than the external one (0–5%). Heavy metals were only found in the most external fraction. Deoxynivalenol contamination decreased from the external to the internal layers: 64% of total contamination of kernel was found in the 0–5% and 5–10% fractions. The 10–15% kernel fraction offered the best compromise between high nutritional value and low contamination risk.     

Weighted Radial Basis Functions for improved pattern recognition and signal processing

The paper describes an improved version of the Radial Basis Function algorithm, which integrates the advantages of Multi-Layer Perceptrons and Radial Basis Functions alone. The proposed paradigm is more general in nature, since it has the other two as particular subcases. It finds applications in several pattern recognition and classification tasks. Furthermore it can also be used as a method to map Fuzzy Inference Systems on Artificial Neural Networks.     

Neural networks-extraordinary variation

There is an extraordinary variation in the implementations of neural networks, ranging from electronic circuits, digital or analog, to novel devices and optical implementations. To provide a wide perspective of different developments, we selected four projects to summarize. These projects were originally presented at Microneuro 1994. The first two projects are optical and optoelectronic implementations. While the majority of neural nets are built in silicon, an active research community works on optical networks. The high connectivity of neural nets makes communication among the processors one of the main difficulties in implementation. With optical beams, a large number of elements can be addressed in parallel, making optics an attractive alternative to silicon. D.C. Burns and coauthors describe a combination of optics and electronics. The authors have built an optical input plane for a neural net so that whole images with tens of thousands of pixels can be entered into a network in parallel. S.R. Skinner, J.E. Steck, and E.C. Behrman present an all optical network, where optically nonlinear materials perform not only the communication but also the calculations. Learning remains a tricky problem for a hardware implementation, in particular for analog circuits. Popular learning algorithms, such as backpropagation, require a high computational resolution. How to implement learning techniques in low-resolution electronics is the subject of intense research. G. Cairns and L. Tarassenko address this issue by comparing the required precision for different learning schemes. The final project is a digital circuit implementing a self-organizing feature map, an unsupervised learning technique. In this example, computational resolution is also a major problem. Before building a chip, researchers experimented extensively to determine the minimum resolution required for good results     

Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign

This paper presents an annotated overview of existing hardware implementations of artificial neural and fuzzy systems and points out limitations, advantages, and drawbacks of analog, digital, pulse stream (spiking), and other implementation techniques. We analyze hardware performance parameters and tradeoffs, and the bottlenecks which are intrinsic in several implementation methodologies. The constraints posed by hardware technologies onto algorithms and performance are also described. The results of the analyses proposed lead to the use of hardware/software codesign, as a means of exploiting the best from both hardware and software techniques. Hardware/software codesign appears, at present, the most promising research area concerning the implementation of neuro-fuzzy systems (not including bioinspired systems, which are out of the scope of this work), as it allows the fast design of complex systems with the highest performance/cost ratio.     

A neuro-fuzzy approach to hybrid intelligent control

This paper presents a neuro-fuzzy approach to the development of high-performance real-time intelligent and adaptive controllers for nonlinear plants. Several paradigms derived from cognitive sciences are considered and analyzed in this work, such as neural networks, fuzzy inference systems, genetic algorithms, etc. The different control strategies are also integrated with finite-state automata, and the theory of fuzzy-state automata is derived from that. The novelty of the proposed approach resides in the tight integration of the control strategies and in the capability of allowing a hybrid design. Finally, three practical applications of the proposed hybrid approach are analyzed     

Design and Implementation of the PAPRICA Parallel Architecture

In this paper PAPRICA, a massively parallel coprocessor devoted to the analysis of bitmapped images is presented considering first the computational model, then the architecture and its implementation, and finally the performance analysis. The main goal of the project was to develop a subsystem to be attached to a standard workstation and to operate as a specialized processing module in dedicated systems. The computational model is strongly related to the concepts of mathematical morphology, and therefore the instruction set of the processing units implements basic morphological transformations. Moreover, the specific processor virtualization mechanism allows to handle and process multiresolution data sets. The actual implementation consists of a mesh of 256 single bit processing units operating in a SIMD style and is based on a set of custom VLSI circuits. The architecture comprises specific hardware extensions that significantly improved performances in real-time applications.