Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO₂) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.     

Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET

Silicon - This work presents the analog and RF performance evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET, and the results acquired have been compared...     

AC analysis of nanoscale GME-TRC MOSFET for microwave and RF applications

In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping (N_A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency (f_t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain (Gma), maximum transducer power gain (G_MT), maximum unilateral power gain (MUG), maximum frequency of oscillation (f_MAX) and stern stability factor (K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained.     

Gate Oxide Variability Analysis of a Novel 3 nm Truncated Fin–FinFET for High Circuitry Performance

Silicon - In this work, we examined the analog and circuitry amplifying capacity of our novel 3 nm Truncated Fin Junctionless bulk FinFET (n-type) with two different oxide thicknesses at...     

Effect of structured parameters on the hot-carrier immunity of transparent gate recessed channel (TGRC) MOSFET

In this work, the impact of parameter variation on hot-carrier effect immunity in transparent gate recessed channel (TGRC)—MOSFET based on the hydrodynamic energy transport model have been studied. The parameters of TGRC-MOSFET investigated include the oxide thickness, negative junction depth, and substrate doping. TCAD analysis shows the performance of TGRC-MOSFET in terms of transfer characteristics, transconductance, electric field, electron velocity, electron mobility and electron temperature. The simulation results indicate the improved hot-carrier immunity for TGRC-MOSFET in 30 nm device.

     

Analysis of a Novel Nanoscale Vacuum Channel TF-FinFET

Silicon - Concerned work is solely dedicated to the optimized characteristics of Nanoscale vacuum channel TF (Truncated fin)-FinFET at gate length of 7 nm. NVCTF-FinFET has its own...     

Discrepancies in the hardness data and the role of grinding‐induced surface effects for a porous zirconate ceramic

The conventionally sintered La₂Zr₂O₇ (LZ) ceramic surfaces illustrated notable structural and microstructural changes post grinding and polishing operations. X‐ray diffraction studies confirmed presence of in‐plane compressive strain on polished surfaces; no phase segregation/separation was noted at surface or bulk level. The scanning electron micrographs revealed that the LZ ceramic grains on the polished top surfaces accommodated this strain by changing their size distribution from unimodal (observed for fractured and unpolished LZ surfaces with average size of 1.2 ± 0.5 μm) to a bimodal (with two modes occurring at 270 nm and 840 nm, respectively) distribution. Possibly, this grain size refinement led the pathway for obtaining surprising high hardness when probed via nanoindentation (13.8 GPa at 4 mN load). This hardness data made this 85% dense LZ sample comparable to its high density (>98%) counterpart (13.8 GPa). The hardness values were noted to have a strong dependence on the penetration depth (h_max). For h_max values beyond 500 nm (and loads≥30 mN), the hardness values depicted a significant decline (by one order of magnitude) and lowered down to 1.8 GPa for 30 mN load. The strain‐induced microstructural changes and the strong dependence of the hardness data (with h_max) paves the path for an in‐depth understanding of the mechanism by which the grinding‐induced strain is modifying the grain structures; especially for the smaller (mode I) grains on the polished LZ surface.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Conducting Polymer Based Gas Sensor Using PNIN- Gate All Around - Tunnel FET

Silicon - In the present work, the n + source pocket PIN gate all around tunnel FET (PNIN-GAA-TFET) based gas sensor has been proposed. Various analyte gases such as hexane, methanol,...