Minimizing power dissipation in optical interconnects at low voltage using optimal modulator design

A strong motivation for insertion of optical interconnects in short-distance applications such as chip-to-chip or back-plane communication, apart from high bit rates, is their potential to achieve these bit rates at low power compared to the currently prevalent copper based interconnects. Thus, it is imperative to construct design methodologies which minimize the total optical link power dissipation. We present one such methodology, where we optimize the quantum-well modulators to minimize the power dissipation in modulator-based optical interconnects. In the first part of the paper, the focus is on obtaining the optimal modulator metrics [contrast ration (CR) and insertion loss], which yield the lowest total power (receiver and the modulator). The trends are studied as a function of the input laser power and bit rate. Having obtained the desirable modulator metrics and the corresponding power dissipation, in the second part, the focus is on the feasibility of these metrics in the light of voltage swing constraints. The biggest concern with the modulator based optical link is the low CR, especially at low voltage swing. While studying these concerns, we also provide insight into the physical design of the modulator including, its intrinsic region thickness, pre-bias voltage, and the size and the number of quantum-wells. Specifically, we outline the method to obtain the design parameters, which allows minimum power dissipation with the least laser power. This ultimately yields higher aggregate I/O bandwidth for chip to chip communication in power limited chips.     

A fast algorithm and practical considerations for passive macromodeling of measured/simulated data

Passive macromodeling of high-speed package and interconnect modules characterized by measured/simulated data has generated immense interest during the recent years. This paper presents an efficient algorithm for transient simulation of interconnect networks characterized by measured/simulated data in the presence of other linear and nonlinear devices. A new set of linear constraints are proposed, which help in preserving the passivity of resulting macromodels. Examples are presented to demonstrate the validity and efficiency of the proposed algorithm.     

Structural and electrical measurements of CdZnSe composite

TheI—Vcharacterization and the electrical resistivity of selenium rich Se₈₅Cd_15-xZn_x (x = 0, 3, 7, 11 and 15) system at room temperature have been studied. Samples were obtained using melt cooling technique. So prepared samples were then characterized in terms of their crystal structure and lattice parameter using X-ray diffraction method. The materials were found to be poly crystalline in nature, having zinc blend structure over the whole range of zinc concentration. The measurements ofI—V bdcharacteristics have been carried out at different temperatures from room to 140°C. The electrical resistivity of the samples with composition at room temperature has been found to vary between maximum 2.7 x 10⁸ Ωm and minimum 7.3 x 10⁵ Ωm and shows a maximum at 3 at. wt.% of Zn. The carrier activation energy of the samples with composition has also been determined and found to vary from 0.026 eV to 0.111 eV.     

SiO2 degradation with charge injection polarity

We have investigated gate oxide degradation in metal-oxide-semiconductor (MOS) devices as a function of high-field constant-current stress for charge injection from both gate and substrate. The two polarities are asymmetric: gate injection, where the substrate Si-SiO₂ interface is the collecting electrode for the energetic electrons, shows a higher rate of interface-state generation (ΔD_it) and lower charge-to-breakdown Q_bd. Thus the collecting electrode interface, which suffers primary damage, emerges as a critical degradation site in addition to the injecting electrode interface, which has been the traditional focus. Consistent with a physical-damage model of breakdown, we demonstrate that interfacial degradation is an important precursor of breakdown, and that the nature of breakdown-related damage is physical, such as trap-generation by broken bonds     

Thermal studies of Cr2O3 doped CaCO3-SiO2 (2∶1) system

Mixtures of CaCO₃SiO₂ in 21 molar ratio were subjected separated to thermal analysis with varying concentration of Cr₂O₃ (0.1 to 5%) as dopant. The activation energy (E _a) and enthalpy (H) shows a decreasing trend with 0.1 to 1% Cr₂O₃ and attains a minimum value with 1% dopant. 0.1 to 0.5% Cr₂O₃ helps in the formation of and C₂S, (Cement Chemistry notations, C = CaO, S = SiO₂) phases at 1400° C and above but 1% Cr₂O₃ stabilizes -C₂S phase along with a little free lime and CaCrO₄. A small quantity of CaCrO₄, Cr₂SiO₂ and -C₂S are also formed along with the major phases with 5% Cr₂O₃ indicating that Cr³⁺ can substitute both Ca²⁺ and Si⁴⁺ ions in the C₂S lattice.     

Multi-objective reactive power market clearing in competitive electricity market using HFMOEA

This paper presents an application of a hybrid fuzzy multi-objective evolutionary algorithm (HFMOEA) for solving a highly constraint, mixed integer type, complex multi-objective reactive power market clearing (RPMC) problem for the competitive electricity market environment. In HFMOEA based multi-objective optimization approach, based on the output of a fuzzy logic controller crossover and mutation probabilities are varied dynamically. It enhances stochastic search capabilities of HFMOEA. In multi-objective RPMC optimization framework, two objective functions namely the total payment function (TPF) for reactive power support from generators and synchronous condensers and the total real transmission loss (TRTL) are minimized simultaneously for clearing the reactive power market. The proposed HFMOEA based multi-objective RPMC scheme is tested on a standard IEEE 24 bus reliability test system and its performance is compared with five other multi-objective evolutionary techniques such as MOPBIL, NSGA-II, UPS-EMOA and SPEA-2 and a new extended form of NSGA (ENSGA-II). Applying all these six evolutionary techniques, a detailed statistical analysis using T-test and boxplots is carried out on three performance metrics (spacing, spread and hypervolume) data for RPMC problem. The obtained simulation results confirm the overall superiority of HFMOEA to generate better Pareto-optimal solutions with higher convergence rate as compared to above mentioned algorithms. Further, TPF and TRTL values corresponding to the best compromise solutions are obtained using said multi-objective evolutionary techniques. These values are compared with one another to take better market clearing decisions in competitive electricity environment.     

Classification of patterns representing Apples and Oranges in three-qubit system

The study of the classification of Apples and Oranges in a warehouse has been undertaken in a three-qubit system using the method of repeated iterations in Grover’s algorithm and Ventura’s algorithm separately. Operator describing an inversion about average has been constructed as a square matrix of order eight, the phase inversion operators and corresponding iteration operators for patterns separately representing Apples and Oranges have been derived, and various possible superpositions as the choice for search states for the classification of these patterns have been obtained for starting states consisting of two patterns and a single pattern, respectively. It has been demonstrated that on the second iteration of the exclusion superposition by the corresponding iteration operators, the patterns Apples and Oranges, respectively, are most suitably classified using the Grover’s algorithm. The probabilities of classifications of Apples have also been calculated by using Ventura’s algorithm (Ventura and Martinez in Inf Sci 124:273–296, 2000; Found Phys Lett 12:547–559, 1999) for all the possible superpositions as the search states, and the results have been compared with those of Grover’s algorithm and it has been demonstrated that in general for classification of a given pattern (Apples) in three-qubit system, the Grover’s and Ventura’s algorithms are effective in the cases where the number of patterns in the stored database is larger or smaller, respectively.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

PMOS transistors in LPCVD polycrystalline silicon-germanium films

P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature (⩽600 °C) process or a high-temperature (up to 950°C) process. Poly-SiGe TFT technology allows the use of lower anneal temperatures and shorter anneal times as compared to a poly-Si TFT technology. The devices fabricated show good transistor characteristics after hydrogenation to reduce the number of electrically active traps in their active channel region     

Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossoverbelow 2.5-V supply

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2-μm technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5-μm technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-μm gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V