Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length L_g = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.     

Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications

Conventional planar transistor shows shrinking substrate bias effect at scaled technology. On the other hand, epitaxial delta-doped channel (EδDC) transistor shows substantial amount of substrate bias effect even at 16-nm channel length. This paper unveils the physics behind the substrate bias effect of an n-channel EδDC transistor through Technology Computer Aided Design simulation with analytical justifications. The depletion width for an EδDC transistor very weakly depends upon the applied substrate bias, and with scaling down of channel length, the depletion width insignificantly gets widened. The substrate control over the channel is high so that significant amount of substrate depletion charge terminates on the gate, instead of on the source and the drain. The degradation of threshold voltage roll off and drain-induced barrier lowering coefficient with the increase of substrate bias, is less for the EδDC transistor, compared to that of a conventional halo free transistor. The dependence of the substrate bias sensitivity on the thickness of the low-doped epitaxial layer and concentration of the high-doped layer is explored. The effects of reverse substrate bias on leakage power dissipation and intrinsic delay of EδDC and conventional transistors are discussed.