A precise 90/spl deg/ quadrature OTA-C oscillator tunable in the 50-130-MHz range

We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-/spl mu/m CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided.     

An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters

This paper presents a scheme to accurately tune the quality factor of second-order LC bandpass filters. The information of the magnitude response at the center and one of the cutoff frequencies is used to tune both the amplitude and the quality factor of the filter using two independent yet interacting loops. Furthermore, the synergic interaction between the loops makes the proposed scheme stable and insensitive to the mismatch between the input amplitudes. A chip prototype was implemented in a 0.35-mum CMOS process and consumes 4.3 mA from a single 1.3-V supply. Measurement results show that at 1.97 GHz the quality factor is tunable from 60 to 220 while the amplitude is tunable between -15 and 0 dBm with worst case quality factor and amplitude tuning accuracies of 10% and 7%, respectively     

The Stochastic I-Pot: A Circuit Block for Programming Bias Currents

In this brief, we present the "stochastic I-Pot." It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38% (8 bits) for currents varying from 176 muA to 19.6 pA. Temperature effects are characterized.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

Insulin resistance in patients with a recent diagnosis of coronary artery disease

Insulin increases limb blood flow in a time- and dose-dependent manner. This effect can be blocked by inhibiting nitric oxide synthesis. These data raise the possibility that insulin resistance is associated with endothelial dysfunction. To examine whether endothelial function and insulin sensitivity are interrelated we quantitated in vivo insulin-stimulated rates of whole body and forearm glucose uptake at a physiological insulin concentration (euglycaemic hyperinsulinaemic clamp, 1 mU.kg-1.min-1 insulin infusion for 2 h) and on another occasion, in vivo endothelial function (blood flow response to intrabrachial infusions of sodium nitroprusside, acetylcholine, and N-monomethyl-L-arginine) in 30 normal male subjects. Subjects were divided into an insulin-resistant (IR) and an insulin-sensitive (IS) group based on the median rate of whole body glucose uptake (31 +/- 2 vs 48 +/- 1 mumol.kg-1.min-1, p < 0.001). The IR and IS groups were matched for age, but the IR group had a slightly higher body mass index, percentage of body fat and blood pressure compared to the IS group. The IR group also had diminished insulin-stimulated glucose extraction (p < 0.05) compared to the IS group, while basal and insulin-stimulated forearm blood flow rates were identical. There was no difference between the IR and IS groups in the forearm blood flow response to endothelium-dependent (acetylcholine and N-monomethyl-L-arginine) or -independent (sodium nitroprusside) vasoactive drugs. In conclusion, the ability of insulin to stimulate glucose uptake at physiological insulin concentrations and endothelium-dependent vasodilatation are distinct phenomena and do not necessarily coexist.     

On the Design of Second Order Dynamics Reaction-Diffusion CNNs

In this paper, a second order reaction-diffusion equation has been identified which is able to reproduce through parameter setting a rich variety of spatio-temporal behaviors. It has been shown that these behaviors are robust against wide random variations in the equation parameters. We have designed a hardware that implements the log-domain version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables without saturation. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. The correct operation of the hardware has been verified through HSPICE simulations.     

7-decade tuning range CMOS OTA-C sinusoidal VCO

A new operational transconductance amplifier-capacitor (OTA-C) based sinusoidal voltage-controlled oscillator (VCO) has been designed and fabricated. The oscillation frequency of which can be tuned from 74 mHz to 1 MHz. The VCO uses a new OTA whose transconductance is adjusted by using a set of special current mirrors. These current mirrors operate in weak inversion and their gain can be controlled continuously through a gate voltage over many decades. This is the first report of such a wide tuning range for CMOS sinusoidal oscillators. Experimental results are provided     

Precise 90/spl deg/ quadrature current-controlled oscillator tunable between 50-130 MHz

A VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8 /spl mu/m CMOS process is presented. The oscillator is tunable in the frequency range from 50-130 MHz. The two phases produced by the oscillator show an extremely low phase difference error (less than 2/spl deg/ over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.     

A new five-parameter MOS transistor mismatch model

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch Δ&thetas; into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors