Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

Molding and hot forming techniques for fabricating plastic aspheric lenses with high blue-light transmittance

The purpose of this paper is to use micro-electroforming and hot-embossing technology as an alternative to high-cost precision cutting or traditional injection molding in the fabrication of plastic aspheric lenses with high Blu-Ray transmittance. The female dies for the aspheric lenses are fabricated from UV-cured SU-8 polymer via electrostatic attraction. However, SU-8 has a 405 nm Blu-Ray transmittance of only roughly 40–50%, which is not appropriate for use in high-density optical pickup systems. This paper, therefore, uses low stress, low surface roughness, nickel micro-electroforming and molding technologies and employs a micro hot-embossing system to form aspheric lenses with high Blu-Ray transmittance from COC plastic (transmittance: 88% at 405 nm). The resulting lenses have a clear aperture of approximately 1 mm and a numerical aperture of roughly 0.6. The electroforming mold has a roughness of approximately 8 nm as measured by AFM. The roughness of COC (n = 1.53) aspheric lenses after hot-embossing is approximately 146 nm (300 µm × 220 µm) as measured by white light interferometer (WYKO). The shape precision of the hot-embossing COC and original SU-8 (n = 1.67) aspheric lenses can be controlled with approximately 2.638% error. The spot size of the hot-embossed COC and original SU-8 aspheric lenses can be controlled with approximately 11% error. This error should account for the material refractive index difference and the shape error. The roughness and spot size were also tested using different pressing temperatures and forces. This technology could be developed to fabricate lenses in Blu-Ray 405 nm micro-optical systems.     

Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation

Excellent n-channel poly-Si thin-film transistors (poly-Si TFTs) have been formed by using retrograde channel scheme with channel doping implantation and extra counter-doping implantation. As compared to the conventional sample with undoped channel layer, a much smaller leakage current can be achieved by boron-doping the poly-Si channel layer, due to a significantly reduced depletion region. However, the on-state characteristics are degraded. A retrograde channel scheme, implemented by further phosphorus counter-doping the surface of the boron-doped channel layer, is proposed for lowering the channel surface doping concentration without changing the bulk channel doping concentration. By using the retrograde channel scheme, an off-state leakage current as low as that for the normal channel-doping scheme may be achieved, while yielding excellent on-state I-V transfer characteristics.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been pro-posed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (orboron) dopant through the spacer, and then the n+-source/drain (n+-S/D) (or p+-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single n+-S/D (or p+-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme, As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.     

Trench MOS barrier Schottky rectifier formed by counter-doping trench-bottom implantation

A trench MOS barrier Schottky (TMBS) rectifier has been formed by carrying out trench bottom counter-doping implantation for improving the blocking voltage and the device reliability. By additionally implementing a counter-doped region enclosing the trench bottom, the reverse blocking voltage of the conventional TMBS rectifier can be significantly enhanced without considerable degradation of on-state characteristics. In addition, the device reliability can be significantly improved. The large peak electric field in the corner of trench bottom, which limits the blocking voltage of the conventional TMBS rectifier, can be largely alleviated due to charge compensation. Though the counter-doped region enclosing the trench bottom may partly encroach into the mesa region, no considerable deterioration of on-state characteristics is caused. In addition, a too low-dose trench-bottom implantation cannot provide sufficient charge compensation, and a too high-dose trench-bottom implantation would create a large peak electric field below the trench bottom. As a result, a proper trench-bottom implantation may be employed to significantly enhance the blocking voltage without considerable degradation of on-state characteristics.     

Electrical characteristics of textured polysilicon oxide preparedby a low-temperature wafer loading and N2 preannealingprocess

A low-temperature wafer loading and N₂ preannealing process was used to grow a thin textured polysilicon oxide. The polyoxide grown on the heavily doped polysilicon film exhibits less oxide tunneling leakage current and higher dielectric strength when the top electrode is positively biased     

Characterization of thin textured tunnel oxide prepared by thermaloxidation of thin polysilicon film on silicon

In this paper, the characteristics of thin textured tunnel oxide prepared by thermal oxidation of thin polysilicon film on Si substrate (TOPS) are studied. Because of the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at the grain boundaries, the oxidation rate of the TOPS sample is close to that of a normal oxide grown on a (111) Si substrate. Also, a textured Si/SiO₂ interface is obtained. The textured Si/SiO₂ interface results in localized high fields and causes a much higher electron injection rate. The optimum TOPS sample can be obtained by properly oxidizing the stacked α-Si film, independent of the substrate doping level. Also, the optimum TOPS sample exhibits a smaller electron trapping rate and a lower interface state generation rate when compared to the sample from a standard tunnel oxide process. These differences are attributed to a lower bulk electric field and a smaller injection area in the TOPS samples     

Research on electrostatic actuator polymer thin-film for controlling light scattering phenomena

The purpose of this paper is based on micro fabrication technology, while integrating planar waveguide technology and the scattering phenomenon generated by electro-statically actuator thin film, to develop a 2-dimensional display technology capable of being cleared and re-displayed. For thin film displacement, the restoration of inward elasticity needs to be overcome. During thin film displacement, attraction due to suction occurs when coming into contact with light waveguide; electrostatic force and elastic force are restored and mutually balanced, causing display to light up. On the other hand, when input voltage is released, electrostatic force stops and thin film is restored to original position, causing display to darken. The design structure uses SU-8 as supporting posts, and PDMS as the electrostatic thin film suspended above the glass substrate (light waveguide). The experimental results show that a waveguide with an electrode length of 250 μm (sub-pixel length), a micro-post height of 27 μm, and a PDMS film thickness of 16 μm requires an actuator voltage of 314 V; and a micro-post height of 27 μm, and a PDMS film thickness of 8 μm requires an actuator voltage of 189 V. Thus, with an arrayed micro-electrode design, electronic paper and panels with large color display area could be manufactured.     

PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures

Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point toward multicore designs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper presents process-level redundancy (PLR), a software technique for transient fault tolerance, which leverages multiple cores for low overhead. PLR creates a set of redundant processes per application process and systematically compares the processes to guarantee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR uses a software-centric approach to transient fault tolerance, which shifts the focus from ensuring correct hardware execution to ensuring correct software execution. As a result, many benign faults that do not propagate to affect program correctness can be safely ignored. A real prototype is presented that is designed to be transparent to the application and can run on general-purpose single-threaded programs without modifications to the program, operating system, or underlying hardware. The system is evaluated for fault coverage and performance on a four-way SMP machine and provides improved performance over existing software transient fault tolerance techniques with a 16.9 percent overhead for fault detection on a set of optimized SPEC2000 binaries.