Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

The Journal of Supercomputing - General-purpose graphics processing units (GPGPUs) are extensively used in high-performance computing. However, it is well known that these devices’...     

Pitfalls of processed pseudogenes in RT-PCR

The patient was a 72-year-old female who had Stage IVb advanced gastric cancer with Virchow's and paraaortic lymph node metastases. She was considered nonresectable and placed on neoadjuvant chemotherapy consisting of low-dose CDDP and 5-FU. After 1 course of administration, Virchow's metastasis disappeared, and the tumor was remarkably reduced in size. However, this chemotherapy was interrupted by toxicity of grade 3 appetite loss, nausea and vomiting, so that total gastrectomy and splenectomy were performed, which were non-curative operation because of paraaortic lymph node metastases. Histopathological examination of the section of the primary tumor revealed that cancer cells had almost disappeared, and only a few atypical cells remained in the granulation tissue. Eleven months after the surgery, there has been no progression of Virchow's and paraaortic lymph node metastases. Combination chemotherapy of low-dose CDDP and 5-FU appears useful as an inductive approach to advanced gastric cancer.     

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.     

HIV-1 infection of monocyte-derived macrophages reduces Fc and complement receptor expression

Fc receptor (FcR) and complement receptor (CR) expression on HIV-infected monocyte-derived macrophages may be an important determinant of immune function. We studied the effects of HIV-1 infection of macrophages in vitro on FcR and CR expression. Macrophages were infected with HIV-1DV 7 days following isolation, and the expression of Fc gamma RI-III and CR3 were measured at intervals thereafter by flow cytometry. We found a reduction in receptor expression with the percentage of cells expressing FcRI 14 days post infection declining from 77% to 13%, FcRII fell from 96% to 85%, FcRIII from 45% to 9%, and CR3 from 91% to 67% 14 days following infection. As these receptors are important for macrophage function, their down-modulation may contribute to the pathogenesis of HIV-related disease.     

Accumulation of unintegrated circular viral DNA in monocytes and growth-arrested T cells following infection with HIV-1

Cytocidal retrovirus infection is characterized by rapid accumulation of unintegrated viral DNA forms. These are thought to be generated by multiple rounds of reinfection and have been suggested to play a central role in cytopathogenesis. Here we have reviewed the work done in this area with HIV-1, mostly using acutely and chronically infected T cell and monocytic cell lines and in some cases T cells blocked at S phase of the cell cycle by aphidicolin treatment. To these studies, we have compared our findings with HIV-1 infected primary peripheral blood monocyte-derived macrophages and untreated and growth-arrested MT-2 cells, two biologically disparate cell populations. Using 1- and 2-long terminal repeat (LTR) circular forms as indicators of unintegrated viral DNA, we found similar rapid accumulation in both untreated and growth-arrested MT-2 cells. In contrast, we found much lower levels in monocyte/macrophages. Our findings suggest that accumulation of unintegrated viral DNA does not require virus production and reinfection in growth-arrested T cells. The significantly lower levels found in monocyte/macrophages may reflect superinfection resistance, allowing the maintenance of a persistent infection.     

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

Evaluating low-level software-based hardening techniques for configurable GPU architectures

The high processing power of GPUs makes them attractive for safety-critical applications, where transient effects are a major concern, and resilience must be enforced without compromising performance. Configurable softcore GPUs are a recent technology that allows detailed reliability assessment capable of bringing directions to the design of reliable GPU applications. This work investigates the reliability of the register files and the pipeline of a softcore GPU under radiation-induced faults. It proposes software-based fault tolerance techniques to mitigate errors. Faults are simulated at the register transfer level in four case-study algorithms, and the Architectural Vulnerability Factor (AVF) and Mean Workload to Failure (MWTF) are checked over different GPU configurations. Results indicate that software-based techniques efficiently reduce AVF. In terms of MWTF, results show that the best cases depend on an optimized balance between GPU configuration, application runtime, and AVF.