Analysing the operation of the basic pass transistor structure

Pass transistor logic has become important for the design of low‐power high‐performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters. Copyright © 2006 John Wiley & Sons, Ltd.     

Design Guidelines for Deadlock-Handling Strategies in Flexible Manufacturing Systems

Deadlock-free operation of flexible manufacturing systems (FMSs) is an important goal of manufacturing systems control research. In this work, we develop the criteria that real-time FMS deadlock-handling strategies must satisfy. These criteria are based on a digraph representation of the FMS state space. Control policies for deadlock-free operation are characterized as partitioning cuts on this digraph. We call these structural control policies (SCPs) because, to avoid deadlock, they must guarantee certain structural properties of the subdigraph containing the empty state; namely, that it is strongly connected. A policy providing this guarantee is referred to as correct. Furthermore, an SCP must be configurable and scalable; that is, its correctness must not depend on configuration-specific system characteristics and it must remain computationally tractable as the FMS grows in size. Finally, an SCP must be efficient; that is, it must not overly constrain FMS operation. We formally develop and define these criteria, formulate guidelines for developing policies satisfying these criteria, and then provide an example SCP development using these guidelines. Finally, we present an SCP that guarantees deadlock-free buffer space allocation for FMSs with no route restrictions.     

A simple cost-effective sputtering-based method for micropatterning and materials microstructuring

Patterning of semiconductors results in the fabrication of micro- and nano-structures, which are desired in modern technologies. Such a patterning is usually realized with the help of e-beam-, high-energy ion-, X-ray- or laser-assisted techniques, which demand expensive equipments. In this work we present a simple cost-effective method realized via a radio-frequency driven magnetron-sputtering head in high vacuum. The target is a silicon wafer masked with metallic grids. If the grid is magnetic, e.g., nickel, it is attracted by the magnetic forces of the magnetron, otherwise, magnetic clamps are used. Soft sputtering conditions, i.e., 30-100 Watts are used and the result is a well-ordered micropatterning of the surface with nicely formed pits the size of which is entirely determined by the grid size and the depth by the sputtering power and time. The pits are monitored with the help of Optical and Atomic Force Microscopy. If the masked micropatterned silicon wafer is then used as a substrate, the pits may be partially filled by a material. As a first example we present square-like Co microstructures. The magnetic signal of these Co microstructures is recorded with the help of a computer-driven magneto-optic Kerr effect home-made magnetometer. This patterned material may be used in magnetic recording technology. More examples include the formation of Cu-microcolumns and Pt film microframeworks. For the latter ones, an etching process is applied to prepare porous silicon networks with photoluminescence, which may be used in optoelectronics.     

Structure and magnetic properties of hcp and fcc nanocrystalline thin Ni films and nanoparticles produced by radio frequency magnetron sputtering

We report on the growth of thin Ni films by radio frequency magnetron sputtering in Ar-plasma. The growth temperature was about 350 K and the films were deposited on various substrates such as glass, silicon, sapphire and alumina. The thickness of the thinnest films was estimated by the appearance of Kiessig fringes up to about 2theta = 8 degrees in the small-angle X-ray diffraction pattern, as expected for high-quality atomically-flat thin films. With the help of this, a quartz balance system was calibrated and used for measuring the thickness of thicker samples with an accuracy of better than 5%. Structural characterization via X-ray diffraction and high resolution transmission electron microscopy revealed an Ar-gas pressure window, where single phase hcp Ni films may be grown. The magnetic response of the Ni films was checked at room temperature via a newly established and fully automatic polar magneto-optic Kerr effect magnetometer. The hcp films show no magnetic response. Interestingly, the magnetic saturation field of fcc films deposited at low Ar pressure is comparable to the one of bulk Ni, while the one of fcc films deposited at high Ar pressures is decreased, revealing the presence of residual strain in the films. Finally, it is shown that it is possible to form films which contain magnetic Ni fcc nanoparticles in a non-magnetic hcp matrix, i.e., a system interesting for technological applications demanding a single Ni target for its production.     

Exchange-Rates Forecasting: A Hybrid Algorithm Based on Genetically Optimized Adaptive Neural Networks

The use of neural networks trained by a new hybrid algorithm is employed on forecasting the Greek Foreign Exchange-Rate Market. Four major currencies, namely the U.S. Dollar (USD), the Deutsche Mark (DEM), the French Franc (FF) and the British Pound (GBP), versus the Greek Drachma, were used as experimental data. The proposed algorithm combines genetic algorithms and a training method based on the localized Extended Kalman Filter (EKF), in order to evolve the structure and train Multi-Layered Perceptron (MLP) neural networks. The goal of this effort is to predict, as accurately as possible, exchange-rates future behavior. Simulation results show that the method gives highly successful results, while the diversification of the structure between the four currencies has no effect on the performance.     

High throughput cellular biosensor for the ultra-sensitive,ultra-rapid detection of aflatoxin M1

The aim of this study was the development of a rapid novel biosensor system based on the Bioelectric Recognition Assay (BERA) for the detection of aflatoxin M1 (AFM1). Membrane-engineering was achieved by electroinsertion of AFM1-homologous antibodies into the membrane of the cells. The sensor measured the electric response of cultured membrane-engineered fibroblast cells suspended in an alginate gel matrix due to the change of their membrane potential after the interaction of the analyte molecules with the antibodies. The BERA-based sensor was able to detect AFM1 rapidly (3min) at very low concentrations (5 pg/ml = 5 ppt), thus demonstrating a higher sensitivity than most currently available biosensor-based methods. In addition, the assay was quite selective against other aflatoxins, such as aflatoxin B1 and ochratoxin A. Furthermore, the assay system allowed for high throughput AFM1 analysis (160 individual tests/h), due to its multiple cell–electrode interface array. Although further research is required for the optimization of the assay, the elimination of possible matrix effects and its validation by assaying actual food samples, this novel biosensor offers new perspectives for ultra-rapid, ultra-sensitive and low-cost monitoring of mycotoxins in food commodities.     

Scalable register bypassing for FPGA-based processors

In this paper, a scalable scheme, configurable via register-transfer level parameters, for full register bypassing in a modern embedded processor architecture, termed ByoRISC, is presented. The register bypassing specification is parameterized regarding the number of homogeneous register file read and write ports and the number of pipeline stages of the processor. The performance characteristics (cycle time, chip area) of the proposed technique have been evaluated for FPGA target implementations of the synthesizable ByoRISC model. It is proved that, a full bypassing network is a viable solution for the elimination of data hazards when servicing instructions with multiple read and write operands. While the maximum clock frequency is reduced by 17.9% in average, when using partial versus full forwarding, the positive effect of custom computation eliminates this effect by providing cycle speedups of 3.9× to 5.5× and corresponding execution time speedups for a ByoRISC testbed processor of 3.6×. Individual application speedups of up to 9.4× have also been obtained.     

GeD spline estimation of multivariate Archimedean copulas

A new multivariate Archimedean copula estimation method is proposed in a non-parametric setting. The method uses the so-called Geometrically Designed splines (GeD splines) to represent the cdf of a random variable W_θ, obtained through the probability integral transform of an Archimedean copula with parameter θ. Sufficient conditions for the GeD spline estimator to possess the properties of the underlying theoretical cdf, K(θ,t), of W_θ, are given. The latter conditions allow for defining a three-step estimation procedure for solving the resulting non-linear regression problem with linear inequality constraints. In the proposed procedure, finding the number and location of the knots and the coefficients of the unconstrained GeD spline estimator and solving the constraint least-squares optimisation problem are separated. Thus, the resulting spline estimator is used to recover the generator and the related Archimedean copula by solving an ordinary differential equation. The proposed method is truly multivariate, it brings about numerical efficiency and as a result can be applied with large volumes of data and for dimensions d≥2, as illustrated by the numerical examples presented.