Impact of the anode operating conditions on the liquid water distribution in the cathode gas diffusion layer

Previous experimental results indicate that the humidification conditions at the anode have an impact on the liquid water distribution in the cathode gas diffusion layer. Numerical simulations are developed to reproduce and analyze this effect. Results consistent with the experimental results are first obtained by playing with the partition coefficients of an advanced pore network model computing the liquid water formation and transfer in the cathode gas diffusion layer (GDL) for a large range of operating conditions. Then, a model for the full anode – cathode assembly is developed by combining the pore network model of the cathode GDL and a 1D model describing the heat and water transfer in the various components of the anode-cathode assembly. This enables one to generalize the dry – wet regime diagram introduced in a previous work by incorporating the effect of the humidity condition at the anode.     

下一代无线网络架构

无线局域网(WLAN)技术为家庭和企业用户描绘了美好的蓝图,也吸引着众多半导体和系统设备厂商涌入这一市场。WLAN技术的不断演变,将标准制订团体、互操作性论坛(互操作性是市场进一步接受的关键要求)、产品OEM厂商和相应的半导体厂商紧密联系在一起。     

Defocusing image to pattern contact holes using attenuated phase shift masks

The patterning of contact holes by selecting out-of-focus image plane (defocus) using attenuated phase shift masks (APSM) has been studied. Defocus is found to enhance the image modulation at low partial coherence for contact holes with negative local average of mask function. Semi-dense holes up to 130 nm in 8% APSM have been printed by 0.5 μm defocus at a partial coherence of 0.31 using KrF scanner with highest numerical aperture of 0.68. However, these holes were closed with in-focus imaging. Defocus is also found to be beneficial for patterning the pitches that have extensive side lobes with in-focus imaging.     

如何用硅振荡器替代晶体和陶瓷谐振器

对于绝大多数微控制器时钟电路而言，硅振荡器是一种简单且有效的解决方案。与晶体和陶瓷谐振器不同，基于硅材料的定时器具有抗振动、抗撞击和抗电磁干扰的优点。同时，硅振荡器不需要严格匹配的定时元件和线路板走线。     

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.