Group parity prediction scheme for concurrent testing of linear feedback shift registers

A group parity prediction scheme which can be used for concurrent testing of linear feedback shift register circuits is described.     

Design of an image edge detection filter using the Sobel operator

The architecture of the edge detector presented is highly pipeline to perform the computations of gradient magnitude and direction for the output image samples. The chip design is based on a 2-μm, double-metal, CMOS technology and was implemented using a silicon compiler system in less than 2 man-months. It is designed to operate with a 10-MHz two-phase clock, and it performs approximately 200×10⁶ additions/s to provide the required magnitude and direction outputs every clock cycle. The function of the chip has been demonstrated with a prototype system that is performing image edge detection in real time     

Testing of differential cascade voltage switch (DCVS) circuits

The problem of testing differential cascode voltage switch (DCVS) circuits is analyzed. These circuits have several potential applications in fault-tolerant, highly available system design due to their inherent self-checking capability. It is shown how concurrent (online) testing of DCVS circuits, which is very effective under single transistor fault assumptions, can be performed. The impact of multiple faults of DCVS circuits is examined, and analytical results are derived. These results indicate that periodic offline tests on DCVS circuits are necessary in order to achieve high multiple-fault coverage. Single-fault test sets and/or pseudorandom vectors were successfully used in the offline tests to detect many of the multiple faults which reduce the efficiency of online tests. The results show the need for a comprehensive mixed-test strategy combining offline and online tests for DCVS circuits     

A built-in test module for fault isolation

A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circuits. The proposed technique is especially useful when boundary scan and self-test cannot be implemented in every chip of a board