Fault-aware Communication Mapping for NoCs with Guaranteed Latency

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.     

(CoFe)Se2@NC超级电容器电极材料的制备及其电化学性能

金属-有机框架(MOF)衍生的过渡金属硒化物和多孔碳纳米复合材料具有巨大的储能优势,是应用于电化学储能的优良电极材料。采用共沉淀法制备CoFe类普鲁士蓝(CoFe-PBA)纳米立方,并通过静电组装在CoFe-PBA上包覆聚吡咯(PPy)得到CoFe-PBA@PPy;通过在400℃氮气中退火并硒化成功制备了氮掺杂的碳(NC)包覆(CoFe)Se₂的(CoFe)Se₂@NC纳米复合材料,并对其结构和形貌进行了表征。以(CoFe)Se₂@NC为电极制备了超级电容器,测试了其电化学性能,结果表明,在电流密度1 A/g时超级电容器的比电容达到1047.9 F/g,在电流密度5 A/g下1000次循环后具有良好的循环稳定性和96.55%的比电容保持率。由于其性能优越、无毒、成本低和易于制备,未来(CoFe)Se₂@NC纳米复合材料在超级电容器中具有非常大的应用潜力。     

Modeling and formal verification of embedded systems based on a Petri net representation

In this paper we concentrate on aspects related to modeling and formal verification of embedded systems. First, we define a formal model of computation for embedded systems based on Petri nets that can capture important features of such systems and allows their representation at different levels of granularity. Our modeling formalism has a well-defined semantics so that it supports a precise representation of the system, the use of formal methods to verify its correctness, and the automation of different tasks along the design process. Second, we propose an approach to the problem of formal verification of embedded systems represented in our modeling formalism. We make use of model checking to prove whether certain properties, expressed as temporal logic formulas, hold with respect to the system model. We introduce a systematic procedure to translate our model into timed automata so that it is possible to use available model checking tools. We propose two strategies for improving the verification efficiency, the first by applying correctness-preserving transformations and the second by exploring the degree of parallelism characteristic to the system. Some examples, including a realistic industrial case, demonstrate the efficiency of our approach on practical applications.     

Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems

We present an approach to static priority preemptive process scheduling for the synthesis of hard real-time distributed embedded systems where communication plays an important role. The communication model is based on a time-triggered protocol. We have developed an analysis for the communication delays with four different message scheduling policies over a time-triggered communication channel. Optimization strategies for the synthesis of communication are developed, and the four approaches to message scheduling are compared using extensive experiments.     

Test Time Minimization for Hybrid BIST of Core-Based Systems

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.     

In掺杂对ZnO薄膜结构及光学特性的影响

通过射频反应溅射法在硅衬底上制备了具有c轴择优取向和小晶格失配的In掺杂ZnO薄膜.在室温下测量样品的光致发光(PL)光谱,观察到波长位于415nm(3.02eV)和430nm(2.88eV)附近的蓝紫发光双峰.研究了不同In掺杂量对ZnO薄膜的结构和发光特性的影响.当In片面积为靶总面积的3%时,样品具有高度的c轴择优取向和较小的晶格失配(0.16%);同时在PL谱中观察到波长位于415nm(3.02eV)和433nm(2.86eV)处的强蓝紫光双峰.     

BTD-NICC型氧压机的扩缸再用

针对BTD-NICC型氧压机缸内表面磨损严重的问题,在气缸强度允许的条件下,通过计算证明两次扩大二段缸以降低温升,再两次适当地扩大一段缸来满足氧压机动力平衡是可行的。     

7 000W交流伺服电机输出轴根部断裂原因分析及改进

针对7 000W伺服电机输出轴根部发生的断裂情况,从其输出轴的疲劳极限、结构及尺寸、精度等方面入手,分析了断裂产生的原因,并提出结构改进方案。     

触摸屏专用线性测试仪的设计

介绍了一种采用工控机作为控制核心的触摸屏专用测试仪。着重介绍了设备各部分的设计构成,采用该设备可以自动对不同规格的触摸屏完成相应的参数测量要求。该自动测量仪性能可靠,操作简便、测试精度高、测试自动化程度高,具有一定的推广价值。     

LCVD制备多晶硅膜实验研究

用CWCO_2激光诱发SiH_4反应,在石英基片上淀积多晶硅膜,它的Raman谱表明,激光诱发反应时间越长,结晶度越高.SEM 结果表明,不同淀积时间,表面结构差异较大.薄厚台阶仪测出不同实验条件淀积速率变化的规律.同时,结合不同条件下控制过程的反应机制,对结果进行了定性的讨论.