Modified register-exchange Viterbi decoder for low-power wireless communications

In this paper, a new implementation of the Viterbi decoder (VD), based on a modified register-exchange (RE) method, is proposed. Conceptually, the RE method is simpler and faster than the trace-back (TB) method. However, the disadvantage of the RE method is that every bit in the memory must be read and rewritten for each bit of information decoded. The proposed implementation adopts the "pointer" concept: a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointer which points to the first register is altered to point to the second register. Power-dissipation, performance, memory size, and the speed of the survivor sequence management are analyzed for both the TB method, and the proposed RE method. The analysis indicates an average power reduction of 23% for the new VD, compared to the power dissipation of the VD described in the literature for the third generation of wireless applications. The bit-error rate is 10/sup -5/ with a signal-to-noise ratio of approximately 6.3 dB for a continuous, uncontrolled encoded sequence. Moreover, the memory requirements of the new implementation are reduced by half. All the read and write operations in the survivor sequence management are executed at the data rate frequency which increases the maximum frequency.     

The digi-neocognitron: a digital neocognitron neural network modelfor VLSI

One of the most complicated ANN models, the neocognitron (NC), is adapted to an efficient all-digital implementation for VLSI. The new model, the digi-neocognitron (DNC), has the same pattern recognition performance as the NC. The DNC model is derived from the NC model by a combination of preprocessing approximation and the definition of new model functions, e.g., multiplication and division are eliminated by conversion of factors to powers of 2, requiring only shift operations. The NC model is reviewed, the DNC model is presented, a methodology to convert NC models to DNC models is discussed, and the performances of the two models are compared on a character recognition example. The DNC model has substantial advantages over the NC model for VLSI implementation. The area-delay product is improved by two to three orders of magnitude, and I/O and memory requirements are reduced by representation of weights with 3 bits or less and neuron outputs with 4 bits or 7 bits.     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

Adaptive sorting: an information theoretic perspective

We present two algorithms that are near optimal with respect to the number of inversions present in the input. One of the algorithms is a variation of insertion sort, and the other is a variation of merge sort. The number of comparisons performed by our algorithms, on an input sequence of length n that has I inversions, is at most . Moreover, both algorithms have implementations that run in time . All previously published algorithms require at least comparisons for some c > 1. M. L. Fredman was supported in part by NSF grant CCR-9732689.     

On the hierarchy of distribution-sensitive properties for data structures

In this paper new dependencies are added to the hierarchy of the distribution-sensitive properties for data structures. Most remarkably, we prove that the working-set property is equivalent to the unified-bound property; a fact that had gone unnoticed since the introduction of such bounds in the Eighties by Sleator and Tarjan.     

Influence of Chemical Reaction on Mass Transport in Yield Stress Exhibiting Flow Regime

Theoretical Foundations of Chemical Engineering - In this study, the simulations for first-order chemical reactions (constructive and destructive) in the flow of the Casson fluid with...     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

Two-tier relaxed heaps

We introduce a data structure which provides efficient heap operations with respect to the number of element comparisons performed. Let n denote the size of the heap being manipulated. Our data structure guarantees the worst-case cost of O(1) for finding the minimum, inserting an element, extracting an (unspecified) element, and replacing an element with a smaller element; and the worst-case cost of O(lg n) with at most lg n + 3 lg lg n + O(1) element comparisons for deleting an element. We thereby improve the comparison complexity of heap operations known for run-relaxed heaps and other worst-case efficient heaps. Furthermore, our data structure supports melding of two heaps of size m and n at the worst-case cost of O(min {lg m, lg n}). A preliminary version of this paper [8] was presented at the 17th International Symposium on Algorithms and Computation held in Kolkata in December 2006. Partially supported by the Danish Natural Science Research Council under contracts 21-02-0501 (project Practical data structures and algorithms) and 272-05-0272 (project Generic programming—algorithms and tools).     

Integration of algorithmic VLSI synthesis with testabilityincorporation

A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary-tree data structure is used throughout the testable design search. Its bottom-up and top-down algorithms provide data-path allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary-tree structure provide VLSI design floorplans and global information for test incorporation. A differential equation and elliptical wave filter example were used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple-chain scan paths and BIST (built-in self-test) with different test schedules were explored. Design scores comprised of area, delay, fault coverage, and test time were computed and graphed