Distributed Arithmetic based Split-Radix FFT

In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.     

Structural Modifications and Extended Spectral Response of CeO2/CoPc Nanocomposites for Potential Applications

CeO₂/CoPc nanocomposites were synthesized by simple chemical method. Thermal behavior of these nanocomposites was studied by thermogravimetric and differential thermal analysis. The as‐synthesized nanocomposite samples were characterized by various techniques. A decrease in band‐gap energy together with an improved absorption intensity of the composite material confirms the role of the cobalt phthalocyanine in the absorption properties of CeO₂/CoPc composite. This study confirms structural modifications and extended spectral response of the synthesized CeO₂/CoPc nanocomposites. The results demonstrate that CeO₂/CoPc nanocomposite samples are promising materials for organic light‐emitting diodes, solar cells, and optoelectronic devices.     

Efficient optimization of integrated spiral inductor with bounding of layout design parameters

In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimization variables are determined graphically. An enumeration algorithm implemented finds the global optimum layout that gives the highest quality factor in less than 1 s of CPU time with less function evaluations. The optimization method also gives the performance of all possible combinations that results the same inductance value. Subsequently important fundamental tradeoff of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is explored in few seconds. The method also gives other valuable information such as sensitivity of the inductance and quality factor to the layout design parameters. The accuracy of the proposed method is verified using a 3D electromagnetic simulator.     

Characterization of optical, electrical and structural properties of silverphthalocyanine thin films

Silverphthalocyanine thin films are deposited on to glass substrates by thermal evaporation technique. Optical data have been obtained from both absorption and reflectivity spectra over the wavelength range 350–900 nm. The absorption coefficient α and extinction coefficient k are estimated from the spectrum. The mechanism of optical absorption follows the rule of direct transition. Using α and k, the refractive index and the dielectric constants are determined. Electrical conductivity studies are done at different substrate temperatures and using the Arrhenius plot the activation energy in the intrinsic region and impurity region is estimated. From the X-ray diffractograms of AgPc thin films subjected to heat treatments the variation of grain size is also studied. The scanning electron microscopy images are taken to study the surface morphology of the films. Silver phthalocyanine thin film is expected to find application in the fabrication of organic transistors and LED devices.     

Improvement in electrical characteristics of ultrathin thermally grown SiO/sub 2/ by selective anodic oxidation

The presence of weak spots and pinholes in ultrathin gate oxides significantly increases the leakage current, thereby degrading the device performance. This paper proposes a method, which identifies the weak spots in thermally grown gate oxide and repairs them by selective anodization. By controlling the applied voltage, it is ensured that current flows only through the weak spots in the oxide during anodization. Anodic oxide therefore grows over these weak spots, improving the reliability of the oxide without increasing the gate oxide thickness. Significant improvement in electrical characteristics was observed in the gate oxides treated by anodic oxidation.     

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f _res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65–95% over conventional planar symmetric inductors and 71–94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC’s will be reduced significantly.     

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson’s equation using “variable separation technique”. The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.     

A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.