Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

Systematic characterization of Cl2 reactive ion etchingfor improved ohmics in AlGaN/GaN HEMTs

Pre-metal-deposition reactive ion etching (RIE) was performed on an Al_0.3Ga_0.7N/AlN/GaN heterostructure in order to improve the metal-to-semiconductor contact resistance. An optimum AlGaN thickness for minimizing contact resistance was determined. An initial decrease in contact resistance with etching time was explained in terms of removal of an oxide surface layer and/or by an increase in tunnelling current with the decrease of the AlGaN thickness. The presence of a dissimilar surface layer was confirmed by an initial nonuniform etch depth rate. An increase in contact resistance for deeper etches was experienced. The increase was related to depletion of the two-dimensional (2-D) electron gas (2-DEG) under the ohmics. Etch depths were measured by atomic force microscopy (AFM). The contact resistance decreased from about 0.45 Ωmm for unetched ohmics to a minimum of 0.27 Ωmm for 70 Å etched ohmics. The initial thickness of the AlGaN layer was 250 Å. The decrease in contact resistance, without excessive complications on device processing, supports RIE etching as a viable solution to improve ohmic contact resistance in AlGaN/GaN HEMTs     

Influence of impact-ionization-induced base current reversal onbipolar transistor parameters

In this paper we describe a set of measurements representing a complete characterization of impact-ionization effects in bipolar transistors. We demonstrate that impact-ionization significantly influences the dependence of base resistance on current and voltages applied to the device. A dc method for the simultaneous extraction of all parasitic resistances in bipolar transistors is presented. The method can separate the influence of current-crowding on the base resistance from that of base width and conductivity modulation; the collector parasitic resistance is measured in the active region. Starting from the parameters extracted by means of these techniques, a complete and accurate circuit-model of impact-ionization effects can be defined     

Comparing and experimenting machine learning techniques for code smell detection

Several code smell detection tools have been developed providing different results, because smells can be subjectively interpreted, and hence detected, in different ways. In this paper, we perform the largest experiment of applying machine learning algorithms to code smells to the best of our knowledge. We experiment 16 different machine-learning algorithms on four code smells (Data Class, Large Class, Feature Envy, Long Method) and 74 software systems, with 1986 manually validated code smell samples. We found that all algorithms achieved high performances in the cross-validation data set, yet the highest performances were obtained by J48 and Random Forest, while the worst performance were achieved by support vector machines. However, the lower prevalence of code smells, i.e., imbalanced data, in the entire data set caused varying performances that need to be addressed in the future studies. We conclude that the application of machine learning to the detection of these code smells can provide high accuracy (>96 %), and only a hundred training examples are needed to reach at least 95 % accuracy.     

Multi-product economic lot scheduling problem with manufacturing and remanufacturing using a basic period policy

In this research we study the multi-product Economic Lot Scheduling Problem (ELSP) with manufacturing and remanufacturing opportunities. Manufacturing and remanufacturing operations are performed on the same production line. Both manufactured and remanufactured products have the same quality thus they fulfil the same demand stream. Tang and Teunter (2006) firstly studied this type of Economic Lot Scheduling Problem with Returns (ELSPR) and presented a complex algorithm for the optimal solution. More recently Teunter, Tang, and Kaparis (2009) proposed several heuristics to deal with the same problem using more computational efficient approaches. However, both studies have limited the attention to the common cycle policy with the assumption that a single (re)manufacturing lot is used for each item in each cycle. Relaxing the constraint of common cycle time and a single (re)manufacturing lot for each item in each cycle, we propose a simple, easy to implement algorithm, based on Segerstedt (1999), to solve the model using a basic period policy. Several numerical examples show the applicability of the algorithm and the cost savings.     

Light emission in AlGaAs/GaAs HEMTs and GaAs MESFETs induced by hotcarriers

Light emission in submicrometer gate AlGaAs/GaAs HEMTs and GaAs MESFETs has been observed at high drain bias values (>4.0 V). The spectral distribution of the emitted photons in the 1.7-2.9-eV range does not correspond to a simple Maxwellian distribution function of the electron energies in the channel. Light emission is observed in correspondence with nonnegligible gate and substrate hole currents, due to the collection of holes generated by impact ionization     

Development of “kink” in the output I–V characteristics of pseudomorphic hemt's after hot-electron accelerated testing

Large decreases in the drain current in the linear and low V_ds region followed by a “kink” in the output I_d-V_ds characteristics have been found after hot electron stress test in AlGaAs/InGaAs/GaAs power pseudomorphic HEMT's. Decrease in the transconductance measured in linear region, increase in the drain parasitic resistance and trasconductance frequency dispersion have also been observed and attributed to the generation of electron traps in the gate-to-drain access region.     

Accelerated Life Test of High Brightness Light Emitting Diodes

Short-term accelerated life test activity on high brightness light emitting diodes is reported. Two families of 1-W light-emitting diodes (LEDs) from different manufacturers were submitted to distinct stress conditions: high temperature storage without bias and high dc current test. During aging, degradation mechanisms like light output decay and electrical property worsening were detected. In particular, the degradation in light efficiency induced by thermal storage was found to follow an exponential law, and the activation energy of the process was extrapolated. Aged devices exhibited a modification of the package epoxy color from white to brown. The instability of the package contributes to the overall degradation in terms of optical and spectral properties. In addition, an increase in thermal resistance was detected on one family of LEDs. This increase induces higher junction temperature levels during operative conditions. In order to correlate the degradation mechanisms and kinetics found during thermal stress, a high dc current stress was performed. Results from this comparative analysis showed similar behavior, implying that the degradation process of dc current aged devices is thermal activated due to high temperatures reached by the junction during stress. Finally, the different effects of the stress on two families of LEDs were taken into account in order to identify the impact of aging on device structure.