多晶硅/氧化硅/多晶硅非平面结构中Fowler-Nordheim隧穿及氧化层退化研究(英文)

Fowler-Nordheim隧穿被广泛应用于EEPROM和闪存中的擦除操作。多晶硅到多晶硅的F-N隧穿具有较高的隧穿效率。本论文基于分栅闪存存储器的结构,对于多晶硅/隧穿氧化层/多晶硅非平面结构的F-N隧穿及其引起的氧化层退化进行了研究。相比于平面结构,非平面结构显示出更高的F-N隧穿效率,且隧穿效率还可通过降低氧化层厚度或者增加预热氧化处理的方法进一步提高。较低的F-N隧穿电流密度显示出较慢的隧穿氧化层退化速率。降低氧化层厚度或者增加热氧化处理也可减缓隧穿氧化层的退化。另外,论文还讨论了研究结果对于改善分栅闪存擦除特性以及耐久性的意义。     

0.18微米三重自对准分栅闪存擦除电压对耐久性的影响

本论文对0.18微米三重自对准分栅闪存中擦除电压对耐久性的影响进行了研究。为了得到最好的耐久性,擦除电压需要进行合适的优化。由于隧穿氧化层会在编程/擦除循环过程中产生电荷陷阱并俘获电荷从而降低浮栅电势,过低的擦除电压会增加闪存单元电流对于浮栅电势变化的敏感性,从而造成更严重的耐久性退化。同时,过高的擦除电压会在选择栅氧化层中产生陷阱电荷,从而也会造成更严重的耐久性退化。论文同时提出了一种擦除电压递增的方法并进行了验证。这种方法能够更好地在两种耐久性退化机制之间进行平衡,从而进一步改善耐久性。     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

正The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

一种新颖的对称式,双比特位,分栅闪存结构单元

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.     

多晶硅栅耗尽导致的SRAM单比特位失效分析

本文分析了一种静态随机存储器单比特位失效的机理.通过纳米探针测量,发现该比特位写操作失败是由负责存取的N型晶体管的驱动力较弱导致.TEM分析显示该晶体管的多晶硅栅中晶粒尺寸较大,这有可能导致栅的功函数变化以及靠近栅介质层区域的掺杂较轻.我们用SPICE模拟证实了晶体管驱动力变弱的原因是局域的多晶栅耗尽.     

利用ISSG退火改善隧穿氧化层的厚度均匀性

利用ISSG低压退火法来取代传统的氧气退火法,对沉积后的隧穿氧化薄膜进行退火处理.由于其独特的可控补偿氧化生长机制,最终在晶圆表面形成了厚度均匀的氧化层,薄膜质量也有了较大改善.这一结果为低压化学汽相沉积得到的隧穿氧化薄膜的平坦化提供了新思路.